Datasheet

1489
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Table 52-2. SAM4E Datasheet Rev. 11157C 25-Jul-2013 Revision History
Doc. Date Changes
25-Jul-2013
Introduction
In “Features” :
- added information on Two-wire Interface in Peripherals section and Wake-on-LAN for EMAC
- changed operating temperature range to 105°C
Updated Table 1-1 “Configuration Summary” with TWI information
In Section 4. “Package and Pinout”, added the FFPI signals to Table 4-1 “SAM4E 100-ball TFBGA Pinout”, Table 4-2
“SAM4E 144-ball LFBGA Pinout”, Table 4-3 “SAM4E 100-lead LQFP Pinout” and Table 4-4 “SAM4E 144-lead LQFP
Pinout”.
Updated Section 5.5 “Low-power Modes”. Added information on WFE.
In Section 6.1 “General Purpose I/O Lines” on page 21, added information on GPIOs as analog input.
Removed Section 7. “Processor and Architecture”. Removed Sections 11-4 to 11-16. Reordered introduction sections.
Removed Note regarding PIOs and 144-pin package at bottom of Table 11-5, “Multiplexing on PIO Controller D (PIOD),”
on page 40 and Table 11-6, “Multiplexing on PIO Controller E (PIOE),” on page 41.
RSTC:
In Section 15.3.6 “Reset Controller Status Register”, RSTTYP information corrected.
RTT:
Added notes in Section 16.4 “Functional Description”, Section 16.5.1 “Real-time Timer Mode Register” and in Section
16.5.2 “Real-time Timer Alarm Register”.
RTC:
In Section 18.5.3 “Alarm”, added new information and note.
In Section 18.5.7 “RTC Accurate Clock Calibration”, updated information on temperature range.
In Section 18.6.5 “RTC Time Alarm Register” and Section 18.6.6 “RTC Calendar Alarm Register”, added notes.
WDT:
In Section 19.1 “Description”, added information on slow clock at 32 kHz.
In Section 19.2 “Embedded Characteristics”, added that Watchdog Clock is independent from Processor Clock.
Moved note (WDD, WDV) from Section 19.5.3 “Watchdog Timer Status Register” to Section 19.5.2 “Watchdog Timer
Mode Register”.
EFC:
In Section 22.4.3.5 “Lock Bit Protection”, added notes on FARG exceeding limits. Updated existing note in Section
22.4.3.6 “GPNVM Bit”.
Added Section 22.4.3.3 “Optimized Partial Programming”. Added note on programming limitations in Section 22.4.3.2
“Write Commands”.
FFPI:
Removed information throughout on Serial Fast Flash Programming not available for device.
CMCC:
In
Table 24.5 “Cortex M Cache Controller (CMCC) User Interface”, up
dated reset value of CMCC_SR.