Datasheet

1485
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
12-Jun-2014
Section 39. “Timer Counter (TC)”
Editorial and formatting changes throughout
Master clock” or “MCK” replaced with “peripheral clock”.
Removed references to FILTER bit (register bit 19 now reserved in Section 39.7.16 “TC Block Mode Register”)
Figure 39-16 “Synchronization with PWM” added value ‘1’ to all multiplexers
Figure 39-18 “Input Stage”: replaced “FILTER” with “MAXFILTER > 0”
Updated Figure 39-1 “Timer Counter Block Diagram”
Updated Figure 39-5 “Example of Transfer with PDC”
Erroneous description of TCCLKS table, rows 0 to 4 reworked in Section 39.7.2 “TC Channel Mode Register:
Capture Mode” and Section 39.7.3 “TC Channel Mode Register: Waveform Mode””
Updated Section 39.7.16 “TC Block Mode Register”
Section 39.6.16.3 “Direction Status and Change Detection”: rewrote sixth paragraph for clarity
Section 39.6.16.4 “Position and Rotation Measurement” rewrote first paragraph for clarity
Section 39.6.16.3 “Direction Status and Change Detection” replaced sentence “The speed can be read on
TC_RA0 register in TC_CMR0” with “The speed can be read on field RA in register TC_RA0”
Added Section 39.6.16.6 “Missing Pulse Detection and Auto-correction”
Added configuration bit AUTOC in Section 39.7.16 “TC Block Mode Register”
Section 39.6.18 “Register Write Protection” changed title (was “Write Protection System”); revised content
Section 39.7.22 “TC Write Protection Mode Register”: modified register name (was “TC Write Protect Mode
Register”); updated WPEN field description (replaced list of protectable registers with link to Section 39.6.18
“Register Write Protection”)
Replaced “0xFFFF” with “2
n-1” (with “n” representing counter size) in Section 39.6.12.1 “WAVSEL = 00”,
Section 39.6.12.3 “WAVSEL = 01”, Figure 39-10 “WAVSEL = 10 without Trigger”, Section 39-14 “WAVSEL =
11 without Trigger”, Figure 39-11 “WAVSEL = 10 with Trigger” and Figure 39-15 “WAVSEL = 11 with Trigger”:
Section 40. “Pulse Width Modulation Controller (PWM)”
Editorial and formatting changes throughout.
Updated Table 40-4 “Fault Inputs”
Modified Section 40.6.2.2 “Comparator”
Section 40.6.6 “Register Write Protection”: at end of section, replaced sentence “The WPVS and PWM_WPSR
fields are automatically reset after reading the PWM_WPSR register” with “The WPVS and WPVSRC fields are
automatically cleared after reading the PWM_WPSR”
Section 40.7.9 “PWM Sync Channels Mode Register”: removed table row for value 3 “reserved” in UPDM field
description
WPKEY/WPCMD are now described with tables in Section 40.7.34 “PWM Write Protection Control Register”
Corrected reset value of PWM_FPV2 in Table 40-7 “Register Mapping” (was 0x0000_0000; is 0x003F_003F)
Deleted instances of “(fault input bit varies from 0 to Z-1)” from field descriptions in Section 40.7.24 “PWM Fault
Mode Register”, Section 40.7.25 “PWM Fault Status Register” on page 1075, Section 40.7.26 “PWM Fault
Clear Register” and Section 40.7.28 on page 1078
Updated Section 40.7.34 “PWM Write Protection Control Register” on page 1084
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued)
Doc. Date Changes