Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1484
12-Jun-2014
Section 38. “Universal Synchronous Asynchronous Receiver Transmitter (USART)”
Minor formatting and editorial changes throughout
Replaced all references to ‘MCK’ with ’peripheral clock’
Modified Figure 38-1 “USART Block Diagram”: Removed ‘SLCK’. Added ‘Bus clock’.
Section 38-2 “I/O Line Description”: removed sentences: ‘Note that it is not recommended to use the USART
interrupt line in edge sensitive mode.’ and ‘Configuring the USART does not require the USART clock to be
enabled.’
Updated Section 38.2 “Embedded Characteristics”: added bullet: ‘Digital Filter on Receive Line’
Table 38-2 “I/O Line Description”: corrected RXD type from Input to I/O.
Section 38.3 “Block Diagram”: removed table “SPI Operating Mode” (information is already present in Table 38-
2 “I/O Line Description”)
Section 38.7 “Functional Description” Removed list of peripheral characteristics that was redundant with
Section 38.2 “Embedded Characteristics”.
In Section 38.7.3.4 “Manchester Decoder”, updated information on RXIDLEV bit in 4th paragraph.
Section 38.7.5.3 “IrDA Demodulator”: replaced instances of “T” with “t” when used to express time
Section 38.7.8.5 “Character Transmission”: INACK replaced by WRDBT.
Section 38.7.10 “Register Write Protection”: Changed section title and reworked content.
Updated Section 38.8.3 “USART Mode Register”
Section 38-13 “IrDA Baud Rate Error”: added missing units of measure to column headers
In Table 9-1, “Section 38-16 “Register Mapping”” changed register name to Manchester Configuration Register
to be consistent throughout the document.
Section 38.8.18 “USART FI DI RATIO Register” modified FI_DI_RATIO field from 16 bits to 11 bits.
In Section 38.8.21 “USART Manchester Configuration Register”: added RXIDLEV as bit 31 and added bit
description.
Section 38.8.22 “USART Write Protection Mode Register” and Section 38.8.23 “USART Write Protection Status
Register”: Changed register names and modified bit and field descriptions.
Figure 38-37 “Example of RTS Drive with Timeguard”: Figure modified with RTS rising edge prior to start bit
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued)
Doc. Date Changes