Datasheet

1483
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
12-Jun-2014
Section 36. “Two-wire Interface (TWI)”
Minor editorial and formatting changes throughout
Added “Register Write Protection” in Section 36.2 “Embedded Characteristics”
Updated Figure 36-1, “Block Diagram”
Updated Section 36.6 “Product Dependencies”, Section 36.7.3.5 “Master Receiver Mode”, Section 36.7.3.7
“Using the Peripheral DMA Controller (PDC)”
Restructured Section 36.7 “Functional Description”
Table 36-7 “Register Mapping”: replaced TWI_THR reset value “0x00000000” with “–”
Section 36.7.3.3 “Programming Master Mode” added one note
Clock Synchronization in Write Mode” in Section 36.7.5.5 “Data Transfer”: at end of last sentence, changed “in
Read mode” to “in Write mode”
Added Section 36.7.5.6 “Using the Peripheral DMA Controller (PDC) in Slave Mode”
Updated Section 36.7.6 “Register Write Protection” (changed title and content), Section 36.8.1 “TWI Control
Register”
Section 36.8.5 “TWI Clock Waveform Generator Register”: replaced t
mck
with t
peripheral clock
in CLDIV and CHDIV
field descriptions
Modified Section 36.8.6 “TWI Status Register”: replaced the description of “NACK”, used in master mode, with
a new text (address byte is now referenced too)
Updated Section 36.8.7 “TWI Interrupt Enable Register” (added first paragraph)
Section 36.8.8 “TWI Interrupt Disable Register””: removed reset value from this write-only register
Section 36.8.11 “TWI Transmit Holding Register”: removed reset value from this write-only register
Section 36.8.12 “TWI Write Protection Mode Register”: replaced list of protectable registers with link to Section
36.7.6 “Register Write Protection”
Modified Section 36.8.13 “TWI Write Protection Status Register”
Replaced instances of “shift register” with “internal shifter”
Section 37. “Universal Asynchronous Receiver Transmitter (UART)”
Minor editorial/language changes throughout.
Changed ‘MCK’ to ‘peripheral clock’
Updated Figure 37-1, “UART Functional Block Diagram”
Corrected the offset for PDC registers in Section 37.6 “Universal Asynchronous Receiver Transmitter (UART)
User Interface”.
Added Section 37.5.5 “Register Write Protection”, and Section 37.6.10 “UART Write Protection Mode Register”.
Updated Section 37.6 “Universal Asynchronous Receiver Transmitter (UART) User Interface” table with Write
Protection Register.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued)
Doc. Date Changes