Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1482
12-Jun-2014
Section 33. “Controller Area Network (CAN)”
Minor editorial formatting changes throughout
MCK replaced with Peripheral clock
Section 33.6.3 “Interrupt” and Section 33.8.1 “CAN Controller Initialization”: Replaced 2 “AIC” occurences with
“interrupt controller.
Updated Section 33.9.12 “CAN Write Protection Mode Register”
Section 33-10 “Possible Initialization Procedure” replaced instance of “AIC” with “Interrupt Controller”
Table 33-4 “Receive Mailbox Objects”: added missing title
Table 33-5 “Transmit Mailbox Objects”: added missing title
Section 33.7.4.1 “CAN Bit Timing Configuration”: moved three bullets describing the phase segments to
precede the bullet “TIME QUANTAM”
Section 34. “Parallel Input/Output Controller (PIO)”
Minor editorial and formatting changes throughout
Replaced all instances of “PIO clock” and “PIO controller clock” with “peripheral clock”
“MCK” replaced with “Peripheral clock” as needed
Section 34.5.1 “Pull-up and Pull-down Resistor Control” Changed information to specify that pull-up or pull-
down can be set.
Updated Section 34.5.3 “Peripheral A or B or C or D Selection”
Section 34.5.10 “Input Edge/Level Interrupt”: edited, reorganized and reformatted example of interrupt
generation
Figure 34-3 “I/O Line Control Logic”: updated connectivity between clocks and glitch/debouncing filter block;
renamed “Resynchronization Stage” to “Peripheral Clock Resynchronization Stage”
Moved
Section 34.5.15 “I/O Lines Programming Example” to appear before Section 34.5.16 “Register
Write Protection”
Section 34.5.16 “Register Write Protection”: Changed section title and revised content.
Updated Section 34.6.46 “PIO Write Protection Mode Register”, Section 34.6.47 “PIO Write Protection Status
Register”
Section 34.6.51 “PIO Parallel Capture Interrupt Enable Register” added bit configuration values
Section 34.6.52 “PIO Parallel Capture Interrupt Disable Register”: added bit configuration values
Section 34.6.53 “PIO Parallel Capture Interrupt Mask Register”: added bit configuration values
Section 34-6 “Input Debouncing Filter Timing”: inserted “(div_slclk)” under “Divided Slow Clock” waveform label
Section 35. “Serial Peripheral Interface (SPI)”
Reworked content.
MCK replaced with peripheral clock
Updated Section 35.3 “Block Diagram”, Section 35-3 “SPI Transfer Format (NCPHA = 1, 8 bits per transfer)”
and Section 35-4 “SPI Transfer Format (NCPHA = 0, 8 bits per transfer)”
Section 35.2 “Embedded Characteristics”: added bullet “Register Write Protection”
Modified Section 35.7.3 “Master Mode Operations”,
Modified Section 35.7.5 “Register Write Protection”, Section 35.8.10 “SPI Write Protection Mode Register” and
Section 35.8.11 “SPI Write Protection Status Register”
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued)
Doc. Date Changes