Datasheet

1481
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
12-Jun-2014
Section 23. “Cortex M Cache Controller (CMCC)”
Modified access rights for “Cache Controller Monitor Configuration Register” and “Cache Controller Monitor
Enable Register”
Modified reset value for “Cache Controller Monitor Status Register”
Removed reset values for write-only registers
Section 24. “SAM-BA Boot Program for SAM4E Microcontrollers”
Modified frequency values in Section 24.2 “Embedded Characteristics” and Section 24.3 “Hardware and
Software Constraints” (“,” replaced with “.”)
Section 26. “DMA Controller (DMAC)”
Modified Section 26.2 “Embedded Characteristics” (added Section 26.3 “DMA Controller Peripheral
Connections”)
ARB_CFG described with a table in Section 26.8.1 “DMAC Global Configuration Register”
WPKEY described with a table in Section 26.8.19 “DMAC Write Protect Mode Register”
Section 27. “Peripheral DMA Controller (PDC)”
Replaced “on- and/or off-chip” with “target” in Section 27.1 “Description” and Section 27.5.2 “Memory Pointers”.
Added Section 27.3 “Peripheral DMA Controller Connections”
Added last paragraph to Section 27.5.1 “Configuration” specifying that the peripheral clock must be enabled for
a PDC transfer
Section 30. “Power Management Controller (PMC)”
Added Section 29.5.5 “Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator”.
Reworked Section 30.13 “Main Clock Failure Detector” for clarity.
Updated the list of write protected registers
Reworked Section 30.11 “Fast Startup” and added Section 30.12 “Startup from Embedded Flash”
Enhanced Section 30.14 “Programming Sequence”
Section 30.16 “Register Write Protection”: Changed section title and re-worked content.
In Section 30.17.20 “PMC Write Protection Mode Register” and Section 30.17.21 “PMC Write Protection Status
Register”: Changed register names and modified bit and field descriptions.
Updated Figure 29-1, “Clock Generator Block Diagram”, Figure 29-3, “Main Clock Block Diagram”Figure 29-4,
“Divider and PLL Block Di
agram”
Se
ction 30.17.8 “PMC
Clock Generator Main Clock Frequency Register”: Added equation to MAINF
description.
Section 31. “Advanced Encryption Standard (AES)”
Editorial and minor formatting changes throughout
Section 31.4.1 “Operation Modes” updated text at end of section
Restructured Section 31.4.3 “Start Modes” to include Section 31.4.3.3 “DMA Mode”
Restructured Section 31.4.4 “Last Output Data Mode”
Section 31-3 “DMA transfer with LOD = 0”: repositioned rising edge of BTC (channel 0)
Updated Section 31-4 “Last Output Data Mode Behavior versus Start Modes”
In Section 31.6.2 “AES Mode Register”, updated LOD field description:
Section 31.6.2 “AES Mode Register”: updated formula in PROCDLY field description
In Section 31.6.10 “AES Initialization Vector Register x”, updated IV field description.
Section 32. “Chip Identifier (CHIPID)”
Corrected title for Section 32.3 “Chip Identifier (CHIPID) User Interface”
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued)
Doc. Date Changes