Datasheet

1465
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
47.11.8.3 MII Mode
Note: 1. For EMAC output signals, Min and Max access times are defined. The Min access time is the time between the GMDC
falling edge and the signal change. The Max access timing is the time between the GMDC falling edge and the signal
stabilization. Figure 47-29 illustrates Min and Max accesses for EMAC
3
.
Table 47-66. EMAC MII Timings
Symbol Parameter Min (ns) Max (ns)
EMAC
4
Setup for GCOL from GTXCK rising 10 —
EMAC
5
Hold for GCOL from GTXCK rising 10 —
EMAC
6
Setup for GCRS from GTXCK rising 10 —
EMAC
7
Hold for GCRS from GTXCK rising 10 —
EMAC
8
GTXER toggling from GTXCK rising 10
(1)
25
(1)
EMAC
9
GTXEN toggling from GTXCK rising 10
(1)
25
(1)
EMAC
10
GTX toggling from GTXCK rising 10
(1)
25
(1)
EMAC
11
Setup for GRX from GRXCK 10 —
EMAC
12
Hold for GRX from GRXCK 10 —
EMAC
13
Setup for GRXER from GRXCK 10 —
EMAC
14
Hold for GRXER from GRXCK 10 —
EMAC
15
Setup for GRXDV from GRXCK 10 —
EMAC
16
Hold for GRXDV from GRXCK 10 —