Datasheet

1455
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
47.11.3.2 SPI Timings
Notes: 1. 3.3V domain: V
VDDIO
from 2.85V to 3.6V, maximum external capacitor = 40 pF.
2. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20 pF.
Note that in SPI master mode, the SAM4E does not sample the data (MISO) on the opposite edge where the data clocks
out (MOSI), but the same edge is used. See Figure 47-19 and Figure 47-20.
Table 47-57. SPI Timings
Symbol Parameter Conditions Min Max Units
SPI
0
MISO Setup time before SPCK rises (master)
3.3V domain
(1)
11.0 — ns
1.8V domain
(2)
12.5 — ns
SPI
1
MISO Hold time after SPCK rises (master)
3.3V domain
(1)
0—ns
1.8V domain
(2)
0—ns
SPI
2
SPCK rising to MOSI Delay (master)
3.3V domain
(1)
-3.4 3.0 ns
1.8V domain
(2)
-3.2 1.9 ns
SPI
3
MISO Setup time before SPCK falls (master)
3.3V domain
(1)
18.0 — ns
1.8V domain
(2)
19.8 — ns
SPI
4
MISO Hold time after SPCK falls (master)
3.3V domain
(1)
0—ns
1.8V domain
(2)
0—ns
SPI
5
SPCK falling to MOSI Delay (master)
3.3V domain
(1)
-6.4 -1.9 ns
1.8V domain
(2)
-5.9 -2.6 ns
SPI
6
SPCK falling to MISO Delay (slave)
3.3V domain
(1)
3.6 11.9 ns
1.8V domain
(2)
4.2 13.9 ns
SPI
7
MOSI Setup time before SPCK rises (slave)
3.3V domain
(1)
0—ns
1.8V domain
(2)
0—ns
SPI
8
MOSI Hold time after SPCK rises (slave)
3.3V domain
(1)
2.8 — ns
1.8V domain
(2)
2.3 — ns
SPI
9
SPCK rising to MISO Delay (slave)
3.3V domain
(1)
3.8 12.1 ns
1.8V domain
(2)
4.2 13.6 ns
SPI
10
MOSI Setup time before SPCK falls (slave)
3.3V domain
(1)
0—ns
1.8V domain
(2)
0—ns
SPI
11
MOSI Hold time after SPCK falls (slave)
3.3V domain
(1)
2.4 — ns
1.8V domain
(2)
2.5 — ns
SPI
12
NPCS setup to SPCK rising (slave)
3.3V domain
(1)
3.2 — ns
1.8V domain
(2)
3.3 — ns
SPI
13
NPCS hold after SPCK falling (slave)
3.3V domain
(1)
0—ns
1.8V domain
(2)
0—ns
SPI
14
NPCS setup to SPCK falling (slave)
3.3V domain
(1)
3.8 — ns
1.8V domain
(2)
3.3 — ns
SPI
15
NPCS hold after SPCK falling (slave)
3.3V domain
(1)
0—ns
1.8V domain
(2)
0—ns