Datasheet

1383

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

45.7.17 AFEC Channel Calibration DC Offset Register

Name: AFEC_CDOR

Address: 0x400B005C (0), 0x400B405C (1)

Access: Read/Write

This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.

 OFFx: Offset for Channel x, used in Automatic Calibration Procedure

0: No Offset.

1: Centers the analog signal on V

ADVREF

/2 before the gain scaling. The applied Offset is: (G-1)V

ADVREF

where G is the applied gain (see the description of the AFEC_CGR).

Note: When a channel requires calibration, the corresponding OFF bit must be configured to ‘1’ prior to launch of the automatic

calibration.

31 30 29 28 27 26 25 24

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23 22 21 20 19 18 17 16

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15 14 13 12 11 10 9 8

OFF15 OFF14 OFF13 OFF12 OFF11 OFF10 OFF9 OFF8

76543210

OFF7 OFF6 OFF5 OFF4 OFF3 OFF2 OFF1 OFF0