Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1372
45.7.7 AFEC Channel Disable Register
Name: AFEC_CHDR
Address: 0x400B0018 (0), 0x400B4018 (1)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
 CHx: Channel x Disable
0: No effect.
1: Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver-
sion, its associated data and its corresponding EOC and OVRE flags in AFEC_SR are unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0