Datasheet

1371
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
45.7.6 AFEC Channel Enable Register
Name: AFEC_CHER
Address: 0x400B0014 (0), 0x400B4014 (1)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
 CHx: Channel x Enable
0: No effect
1: Enables the corresponding channel
Note: If USEQ = 1 in the AFEC_MR, CHx corresponds to the xth channel of the sequence described in AFEC_SEQ1R,
AFEC_SEQ2R.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0