Datasheet

1351
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
45.6.10 Input Gain and Offset
The AFEC has a built in Programmable Gain Amplifier (PGA) and Programmable Offset per channel (through a
DAC).
The Programmable Gain Amplifier can be set to gains of 1/2, 1, 2 and 4. The Programmable Gain Amplifier can be
used either for single ended applications or for fully differential applications.
If ANACH is set in AFEC_MR, the AFEC can apply different gain and offset on each channel. Otherwise the
parameters of CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain Register (AFEC_CGR) as shown in Table 45-6.
Analog offset of the AFEC can be configured by the AOFF field in the AFEC Channel Offset Compensation
Register (AFEC_COCR). The Offset is only available in Single Ended Mode. When AOFF is configured to 0, the
offset equals 0, when 4095 the offset equals ADVREF-1LSB. All possible offset values are provided between
these two limits according to the following formula: AOFF*(VREF/4096).
Table 45-4. Input Pins and Channel Number in Single Ended Mode
Input Pins Channel Number
AFE_AD0 CH0
AFE_AD1 CH1
... ...
AFE_AD14 CH14
AFE_AD15 CH15
Table 45-5. Input Pins and Channel Number In Differential Mode
Input Pins Channel Number
AFE_AD0-AFE_AD1 CH0
... ...
AFE_AD14-AFE_AD15 CH14
Table 45-6. Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit
GAIN<0:1> GAIN (DIFF = 0) GAIN (DIFF = 1)
00 1 0.5
01 1 1
10 2 2
11 4 2