Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1242
 HRESP: HRESP Not OK
A read of this register returns the value of the HRESP not OK interrupt mask.
0: Interrupt is enabled.
1: Interrupt is disabled.
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt
to be generated if a 1 is written.
 PFNZ: Pause Frame with Non-zero Pause Quantum Received
A read of this register returns the value of the pause frame with non-zero pause quantum interrupt mask.
0: Interrupt is enabled.
1: Interrupt is disabled.
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt
to be generated if a 1 is written.
 PTZ: Pause Time Zero
A read of this register returns the value of the pause time zero interrupt mask.
0: Interrupt is enabled.
1: Interrupt is disabled.
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt
to be generated if a 1 is written.
 PFTR: Pause Frame Transmitted
A read of this register returns the value of the pause frame transmitted interrupt mask.
0: Interrupt is enabled.
1: Interrupt is disabled.
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt
to be generated if a 1 is written.
 EXINT: External Interrupt
A read of this register returns the value of the external interrupt mask.
0: Interrupt is enabled.
1: Interrupt is disabled.
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt
to be generated if a 1 is written.
 DRQFR: PTP Delay Request Frame Received
A read of this register returns the value of the PTP delay_req frame received mask.
0: Interrupt is enabled.
1: Interrupt is disabled.
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt
to be generated if a 1 is written.