Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1232
43.7.8 Transmit Buffer Queue Base Address Register
Name: GMAC_TBQB
Address: 0x4003401C
Access: Read/Write
This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer
Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register.
Once transmission has started, any write to the Transmit Buffer Queue Base Address Register is illegal and therefore
ignored.
Note that due to clock boundary synchronization, it takes a maximum of four MCK cycles from the writing of the transmit
start bit before the transmitter is active. Writing to the Transmit Buffer Queue Base Address Register during this time may
produce unpredictable results.
Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at
once, this may not necessarily be pointing to the current frame being transmitted.
In terms of AMBA AHB operation, the descriptors are written to memory using a single 32-bit AHB access. The descriptors
should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential
accesses.
 ADDR: Transmit Buffer Queue Base Address
Written with the address of the start of the transmit queue.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR – –