Datasheet

1227
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
43.7.5 DMA Configuration Register
Name: GMAC_DCFGR
Address: 0x40034010
Access: Read/Write
 FBLDO: Fixed Burst Length for DMA Data Operations:
Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management oper-
ations and only used where space and data size allow. Otherwise SINGLE type AHB transfers are used.
Upper bits become non-writable if the configured DMA TX and RX FIFO sizes are smaller than required to support the
selected burst size.
One-hot priority encoding enforced automatically on register writes as follows, where ‘x’ represents don’t care:
 ESMA: Endian Swap Mode Enable for Management Descriptor Accesses
When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.
 ESPA: Endian Swap Mode Enable for Packet Data Accesses
When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
DRBS
15 14 13 12 11 10 9 8
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76543210
ESPA ESMA – FBLDO
Value Name Description
0– Reserved
1 SINGLE 00001: Always use SINGLE AHB bursts
2– Reserved
4 INCR4 001xx: Attempt to use INCR4 AHB bursts (Default)
8 INCR8 01xxx: Attempt to use INCR8 AHB bursts
16 INCR16 1xxxx: Attempt to use INCR16 AHB bursts