Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1196
To receive frames, the AHB buffer descriptors must be initialized by writing an appropriate address to bits 31:2 in
the first word of each list entry. Bit 0 must be written with zero. Bit 1 is the wrap bit and indicates the last entry in
the buffer descriptor list.
The start location of the receive buffer descriptor list must be written with the receive buffer queue base address
before reception is enabled (receive enable in the Network Control Register). Once reception is enabled, any
writes to the Receive Buffer Queue Base Address Register are ignored. When read, it will return the current
pointer position in the descriptor list, though this is only valid and stable when receive is disabled.
If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing
data into the receive buffer. If an error occurs, the buffer is recovered.
An internal counter within the GMAC represents the receive buffer queue pointer and it is not visible through the
CPU interface. The receive buffer queue pointer increments by two words after each buffer has been used. It re-
initializes to the receive buffer queue base address if any descriptor has its wrap bit set.
As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the descriptor to
logic one indicating the AHB buffer has been used.
Software should search through the “used” bits in the AHB buffer descriptors to find out how many frames have
been received, checking the start of frame and end of frame bits.
20
Priority tag detected—type ID of 0x8100 and null VLAN identifier. For packets incorporating
the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type
ID of 0x8100 and a null VLAN identifier.
19:17 VLAN priority—only valid if bit 21 is set.
16 Canonical format indicator (CFI) bit (only valid if bit 21 is set).
15
End of frame—when set the buffer contains the end of a frame. If end of frame is not set,
then the only valid status bit is start of frame (bit 14).
14
Start of frame—when set the buffer contains the start of a frame. If both bits 15 and 14 are
set, the buffer contains a whole frame.
13
This bit has a different meaning depending on whether jumbo frames and ignore FCS
modes are enabled. If neither mode is enabled this bit will be zero.
With jumbo frame mode enabled: (bit 3 set in Network Configuration Register) Additional
bit for length of frame (bit[13]), that is concatenated with bits[12:0]
With ignore FCS mode enabled and jumbo frames disabled: (bit 26 set in Network
Configuration Register and bit 3 clear in Network Configuration Register) This indicates per
frame FCS status as follows:
0: Frame had good FCS
1: Frame had bad FCS, but was copied to memory as ignore FCS enabled.
12:0
These bits represent the length of the received frame which may or may not include FCS
depending on whether FCS discard mode is enabled.
With FCS discard mode disabled: (bit 17 clear in Network Configuration Register)
Least significant 12 bits for length of frame including FCS. If jumbo frames are enabled,
these 12 bits are concatenated with bit[13] of the descriptor above.
With FCS discard mode enabled: (bit 17 set in Network Configuration Register)
Least significant 12 bits for length of frame excluding FCS. If jumbo frames are enabled,
these 12 bits are concatenated with bit[13] of the descriptor above.
Table 43-2. Receive Buffer Descriptor Entry (Continued)
Bit Function