Datasheet

1113
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
41.8.4 Write Operation
In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-
multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used.
If set, the bit PDCMODE enables PDC transfer.
The flowchart in Figure 41-9 shows how to write a single block with or without use of PDC facilities. Polling or
interrupt method can be used to wait for the end of write according to the contents of the HSMCI Interrupt Mask
Register (HSMCI_IMR).