Datasheet

1101
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
40.7.50 PWM Channel Additional Edge Update Register
Name: PWM_CAEUPDx [x=0..3]
Address: 0x40000408 [0], 0x40000428 [1], 0x40000448 [2], 0x40000468 [3]
Access: Write-only
This register acts as a double buffer for the ADEDGV and ADEDGM values. This prevents an unexpected waveform when
modifying the additional edge value and the additional edge mode.
Only the first 16 bits (channel counter size) are significant.
 ADEDGVUP: Channel Additional Edge Value Update
Defines the timing of the additional edge. After writing this register, the channel polarity is inverted when the channel coun-
ter reaches the value defined by this field, that leads to an additional edge of the channel output waveform. This value must
be defined between 0 and CPRD (PWM_CPRx). The additional edge occurs only one time after writing this register.
 ADEDGMUP: Channel Additional Edge Mode Update
Note: This field is useless if the counter of the channel x is left aligned (CALG = 0 in PWM Channel Mode Register)
31 30 29 28 27 26 25 24
–––––– ADEDGMUP
23 22 21 20 19 18 17 16
ADEDGVUP
15 14 13 12 11 10 9 8
ADEDGVUP
76543210
ADEDGVUP
Value Name Description
0INC
The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP
and the counter of the channel x is incrementing.
1DEC
The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP
and the counter of the channel x is incrementing.
2BOTH
The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP,
whether the counter is incrementing or not.
3–Reserved