Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1100
40.7.49 PWM Channel Additional Edge Register
Name: PWM_CAEx [x=0..3]
Address: 0x40000404 [0], 0x40000424 [1], 0x40000444 [2], 0x40000464 [3]
Access: Read/Write
Only the first 16 bits (channel counter size) are significant.
 ADEDGV: Channel Additional Edge Value
Defines the timing of the additional edge. After writing this register, the channel polarity is inverted when the channel coun-
ter reaches the value defined by this field, that leads to an additional edge of the channel output waveform. This value must
be defined between 0 and CPRD (PWM_CPRx). The additional edge occurs only one time after writing this register.
 ADEDGM: Channel Additional Edge Mode
Note: This field is useless if the counter of the channel x is left aligned (CALG = 0 in PWM Channel Mode Register).
31 30 29 28 27 26 25 24
–––––– ADEDGM
23 22 21 20 19 18 17 16
ADEDGV
15 14 13 12 11 10 9 8
ADEDGV
76543210
ADEDGV
Value Name Description
0INC
The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and
the counter of the channel x is incrementing.
1DEC
The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and
the counter of the channel x is incrementing.
2BOTH
The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV,
whether the counter is incrementing or not.
3–Reserved