Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1090
40.7.40 PWM Channel Mode Register
Name: PWM_CMRx [x=0..3]
Address: 0x40000200 [0], 0x40000220 [1], 0x40000240 [2], 0x40000260 [3]
Access: Read/Write
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
 CPRE: Channel Pre-scaler
 CALG: Channel Alignment
0: The period is left-aligned.
1: The period is center-aligned.
 CPOL: Channel Polarity
0: The OCx output waveform (output from the comparator) starts at a low level.
1: The OCx output waveform (output from the comparator) starts at a high level.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––DTLIDTHIDTE
15 14 13 12 11 10 9 8
––––UPDSCESCPOLCALG
76543210
–––– CPRE
Value Name Description
0b0000 MCK Peripheral clock
0b0001 MCK_DIV_2 Peripheral clock/2
0b0010 MCK_DIV_4 Peripheral clock/4
0b0011 MCK_DIV_8 Peripheral clock/8
0b0100 MCK_DIV_16 Peripheral clock/16
0b0101 MCK_DIV_32 Peripheral clock/32
0b0110 MCK_DIV_64 Peripheral clock/64
0b0111 MCK_DIV_128 Peripheral clock/128
0b1000 MCK_DIV_256 Peripheral clock/256
0b1001 MCK_DIV_512 Peripheral clock/512
0b1010 MCK_DIV_1024 Peripheral clock/1024
0b1011 CLKA Clock A
0b1100 CLKB Clock B