Datasheet

1051
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
40.7.1 PWM Clock Register
Name: PWM_CLK
Address: 0x40000000
Access: Read/Write
This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the PWM Write Protection Status Register.
 DIVA, DIVB: CLKA, CLKB Divide Factor
 PREA, PREB: CLKA, CLKB Source Clock Selection
31 30 29 28 27 26 25 24
–––– PREB
23 22 21 20 19 18 17 16
DIVB
15 14 13 12 11 10 9 8
–––– PREA
76543210
DIVA
DIVA, DIVB CLKA, CLKB
0 CLKA, CLKB clock is turned off
1 CLKA, CLKB clock is clock selected by PREA, PREB
2–255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
PREA, PREB Divider Input Clock
0000Peripheral clock
0001Peripheral clock/2
0010Peripheral clock/4
0011Peripheral clock/8
0100Peripheral clock/16
0101Peripheral clock/32
0110Peripheral clock/64
0111Peripheral clock/128
1000Peripheral clock/256
1001Peripheral clock/512
1010Peripheral clock/1024
Other Reserved