Datasheet

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1041

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

1050

Notes: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3.

0x19C PWM Comparison 6 Mode Update Register PWM_CMPMUPD6 Write-only –

0x1A0 PWM Comparison 7 Value Register PWM_CMPV7 Read/Write 0x0

0x1A4 PWM Comparison 7 Value Update Register PWM_CMPVUPD7 Write-only –

0x1A8 PWM Comparison 7 Mode Register PWM_CMPM7 Read/Write 0x0

0x1AC PWM Comparison 7 Mode Update Register PWM_CMPMUPD7 Write-only –

0x1B0–0x1FC Reserved – – –

0x200 + ch_num *

0x20 + 0x00

PWM Channel Mode Register

(1)

PWM_CMR Read/Write 0x0

0x200 + ch_num *

0x20 + 0x04

PWM Channel Duty Cycle Register

(1)

PWM_CDTY Read/Write 0x0

0x200 + ch_num *

0x20 + 0x08

PWM Channel Duty Cycle Update Register

(1)

PWM_CDTYUPD Write-only –

0x200 + ch_num *

0x20 + 0x0C

PWM Channel Period Register

(1)

PWM_CPRD Read/Write 0x0

0x200 + ch_num *

0x20 + 0x10

PWM Channel Period Update Register

(1)

PWM_CPRDUPD Write-only –

0x200 + ch_num *

0x20 + 0x14

PWM Channel Counter Register

(1)

PWM_CCNT Read-only 0x0

0x200 + ch_num *

0x20 + 0x18

PWM Channel Dead Time Register

(1)

PWM_DT Read/Write 0x0

0x200 + ch_num *

0x20 + 0x1C

PWM Channel Dead Time Update Register

(1)

PWM_DTUPD Write-only –

0x400 + ch_num *

0x20 + 0x00

PWM Channel Mode Update Register

(1)

PWM_CMUPD Write-only –

0x400 + ch_num *

0x20 + 0x04

PWM Channel Additional Edge Register

(1)

PWM_CAE Read/Write 0x0

0x400 + ch_num *

0x20 + 0x08

PWM Channel Additional Edge Update Register

(1)

PWM_CAEUPD Write-only –

Table 40-7. Register Mapping (Continued)

Offset Register Name Access Reset