Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1038
 ENDTX (not relevant if DMA is used): this flag is set to ‘1’ when a PDC transfer is completed
 TXBUFE (not relevant if DMA is used): this flag is set to ‘1’ when the PDC buffer is empty (no pending PDC
transfers)
 UNRE: this flag is set to ‘1’ when the update period defined by the UPR field has elapsed while the whole
data has not been written by the PDC or DMA. It is reset to ‘0’ when the PWM_ISR2 is read.
Depending on the interrupt mask in the PWM_IMR2, an interrupt can be generated by these flags.
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatic update by setting the field UPDM to 2 in the
PWM_SCM register.
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC or DMAtransfer request must be set in the update
period by the PTRM bit and the PTRCS field in the PWM_SCM register (at the end of the update period or
when a comparison matches).
5. Define the PDC or DMA transfer settings for the duty-cycle values and enable it in the PDC or DMA registers
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write registers that need to be
updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 10.
8. Set UPDULOCK to ‘1’ in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit
UPDULOCK is reset, go to Step 7. for new values.
10. If an update of the update period value is required, check first that write of a new update value is possible by
polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2, else go to Step 12.
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous channels when the Update
Period is elapsed. Go to Step 10. for new values.If DMA is used: Check the end of the DMA transfer by the
flag BTCx in DMA controller. If the transfer has ended, define a new DMA transfer for new duty-cycle values.
Go to Step 5. If PDC is used: Check the end of the PDC transfer by the flag ENDTX. If the transfer has
ended, define a new PDC transfer in the PDC registers for new duty-cycle values. Go to Step 5.
Figure 40-14. Method 3 (UPDM = 2 and PTRM = 0)
CCNT0
CDTYUPD
0x20
0x40
0x60
UPRCNT
0x0
0x1
0x0
0x1
0x0
0x1
CDTY
UPRUPD 0x1
0x3
transfer request
WRDY
0x0
0x1
0x2
0x3
0x0
0x1
0x2
UPR
0x1
0x3
0x80
0xA0
0xB0
0x20
0x40
0x60
0x80
0xA0