Datasheet

1035
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Method 1: Manual write of duty-cycle values and manual trigger of the update
In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by
writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).
To trigger the update, the user must use the bit UPDULOCK in the PWM_SCUC register which allows to update
synchronously (at the same PWM period) the synchronous channels:
 If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels.
 If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed.
After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0.
Sequence for Method 1:
1. Select the manual write of duty-cycle values and the manual update by setting the UPDM field to ‘0’ in the
PWM_SCM register
2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register.
3. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
4. If an update of the period value and/or the duty-cycle values and/or the dead-time values is required, write
registers that need to be updated (PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).
5. Set UPDULOCK to ‘1’ in PWM_SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. At this moment the
UPDULOCK bit is reset, go to Step 4.) for new values.
Table 40-6. Summary of the Update of Registers of Synchronous Channels
UPDM = 0 UPDM = 1 UPDM = 2
Period Value
(PWM_CPRDUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to ‘1’
Dead-Time Values
(PWM_DTUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to ‘1’
Duty-Cycle Values
(PWM_CDTYUPDx)
Write by the CPU Write by the CPU Write by the PDC or DMA
Update is triggered at the next
PWM period as soon as the bit
UPDULOCK is set to ‘1’
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR
Update Period Value
(PWM_SCUPUPD)
Not applicable Write by the CPU
Not applicable
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR