Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1034
The synchronous channels are defined by the SYNCx bits in the PWM Sync Channels Mode Register
(PWM_SCM). Only one group of synchronous channels is allowed.
When a channel is defined as a synchronous channel, the channel 0 is automatically defined as a synchronous
channel too, because the channel 0 counter configuration is used by all the synchronous channels.
If a channel x is defined as a synchronous channel, it uses the following configuration fields of the channel 0
instead of its own:
 CPRE0 field in PWM_CMR0 instead of CPREx field in PWM_CMRx (same source clock)
 CPRD0 field in PWM_CMR0 instead of CPRDx field in PWM_CMRx (same period)
 CALG0 field in PWM_CMR0 instead of CALGx field in PWM_CMRx (same alignment)
Thus writing these fields of a synchronous channel has no effect on the output waveform of this channel (except
channel 0 of course).
Because counters of synchronous channels must start at the same time, they are all enabled together by enabling
the channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by
disabling channel 0 (by the CHID0 bit in PWM_DIS register). However, a synchronous channel x different from
channel 0 can be enabled or disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS
registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to ‘1’
while it was at ‘0’) is allowed only if the channel is disabled at this time (CHIDx = 0 in
PWM_SR). In the same way,
defining a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to ‘0’
while it was 1) is allowed only if the channel is disabled at this time.
The field UPDM (Update Mode) in the PWM_SCM register allow to select one of the three methods to update the
registers of the synchronous channels:
 Method 1 (UPDM = 0): The period value, the duty-cycle values and the dead-time values must be written by
the CPU in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the PWM
Sync Channels Update Control Register (PWM_SCUC) is set to ‘1’ (see “Method 1: Manual write of duty-
cycle values and manual trigger of the update” on page 1035).
 Method 2 (UPDM = 1): The period value, the duty-cycle values, the dead-time values and the update period
value must be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is
triggered at the next PWM period as soon as the bit UPDULOCK in the PWM_SCUC register is set to ‘1’.
The update of the duty-cycle values and the update period value is triggered automatically after an update
period defined by the field UPR in the PWM Sync Channels Update Period Register (PWM_SCUP) (see
“Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 1036).
 Method 3 (UPDM = 2): Same as Method 2 apart from the fact that the duty-cycle values of ALL synchronous
channels are written by the Peripheral DMA Controller (PDC or DMA) (see “Method 3: Automatic write of
duty-cycle values and automatic trigger of the update” on page 1037). The user can choose to synchronize
the PDC or DMAtransfer request with a comparison match (see Section 40.6.3 “PWM Comparison Units”),
by the fields PTRM and PTRCS in the PWM_SCM register. The DMA destination address must be
configured to access only the PWM DMA Register (PWM_DMAR). The DMA buffer data structure must
consist of sequentially repeated duty cycles. The number of duty cycles in each sequence corresponds to
the number of synchronized channels. Duty cycles in each sequence must be ordered from the lowest to the
highest channel index. The size of the duty cycle is 16 bits.