Datasheet

1033
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
one to the bit CPOLINVUP in the same register. In this case the polarity will be inverted synchronously with
the PWM period and the bit CPOLUP is not taken into account.
 By inverting the polarity at a precise moment of the PWM period:
Write the field ADEDGV and the field ADEDGM in the PWM Channel Additional Edge Register. As soon as
the channel counter reaches the value defined by ADEDGV, the polarity of the output waveform is inverted.
The field ADEDGM is used when the channel is center-aligned (CALG = 1 in PWM Channel Mode Register).
̶ If ADEDGM = 0 the additional edge occurs when the channel counter is incrementing.
̶ If ADEDGM = 1 the additional edge occurs when it is decrementing.
̶ If ADEDGM = 2 the additional edge occurs whether the counter is incrementing or not.
 By inverting the polarity at a precise moment of the next PWM period:
Write the field ADEDGVUP and the field ADEDGMUP in the PWM Channel Additional Edge Update
Register. As soon as the channel counter reaches the value defined by ADEDGVUP at the next PWM
period, the polarity of the output waveform is inverted. The field ADEDGMUP is used when the channel is
center-aligned (CALG = 1 in PWM Channel Mode Register):
̶ If ADEDGMUP = 0 the additional edge occurs when the channel counter is incrementing.
̶ If ADEDGMUP = 1 the additional edge occurs when it is decrementing.
̶ If ADEDGMUP = 2 the additional edge occurs whether the counter is incrementing or not.
Figure 40-11 on page 1033 illustrates various ways to insert additional edges on the channel waveform by
inverting the waveform polarity.
Figure 40-11. Inserting Additional Edges on the Output Waveform
40.6.2.9 Synchronous Channels
Some channels can be linked together as synchronous channels. They have the same source clock, the same
period, the same alignment and are started together. In this way, their counters are synchronized together.
CNT (PWM_CCNTx)
CPRD = 14 (PWM_CPRDx)
CDTY = 7 (PWM_CDTYx)
Counter Event
CHIDx (PWM_ISR1)
CPOL (PWM_CMRx)
Output Waveform
OCx
Write CPOL
(PWM_CMRx)
Write CPOLUP
(PWM_CMRUPx)
Write ADEDG/ADEDGM
(PWM_CAEx)
Write ADEDGUP/ADEDGMUP
(PWM_CAEUPx)
CPOL=1
CPOLUP=0
CPOLINVUP=0
CPOLUP=0
CPOLINVUP=1
ADEDG=3
ADEDGM=1
ADEDGUP=10
ADEDGMUP=0
0
3
10