Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1026
 the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is
defined in the CPOL bit of the PWM_CMRx. By default the signal starts by a low level. the waveform
alignment. The output waveform can be left or center-aligned. Center-aligned waveforms can be used to
generate non-overlapped waveforms. This property is defined in the CALG bit of the PWM_CMRx. The
default mode is left-aligned.
Figure 40-4. Non-Overlapped Center-Aligned Waveforms
Note: 1. See Figure 40-5 on page 1027 for a detailed description of center-aligned waveforms.
When center-aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period.
When left-aligned, the channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center-aligned channel is twice the period for a left-aligned
channel.
Waveforms are fixed at 0 when:
 CDTY = CPRD and CPOL = 0
 CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
 CDTY = 0 and CPOL = 0
 CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.
Modifying CPOL in PWM Channel Mode Register while the channel is enabled can lead to an unexpected
behavior of the device being driven by PWM.
In addition to generating the output signals OCx, the comparator generates interrupts depending on the counter
value. When the output waveform is left-aligned, the interrupt occurs at the end of the counter period. When the
output waveform is center-aligned, the bit CES of PWM_CMRx defines when the channel counter interrupt occurs.
If CES is set to ‘0’, the interrupt occurs at the end of the counter period. If CES is set to ‘1’, the interrupt occurs at
the end of the counter period and at half of the counter period.
Figure 40-5 “Waveform Properties” illustrates the counter interrupts depending on the configuration.
OC0
OC1
Period
No overlap