Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1018
40.2 Embedded Characteristics
 4 Channels
 Common Clock Generator Providing Thirteen Different Clocks
̶ A Modulo n Counter Providing Eleven Clocks
̶ Two Independent Linear Dividers Working on Modulo n Counter Outputs
 Independent Channels
̶ Independent 16-bit Counter for Each Channel
̶ Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or
Non-Overlapping Time) for Each Channel
̶ Independent Enable Disable Command for Each Channel
̶ Independent Clock Selection for Each Channel
̶ Independent Period, Duty-Cycle and Dead-Time for Each Channel
̶ Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel
̶ Independent Programmable Selection of The Output Waveform Polarity for Each Channel, with
Double Buffering
̶ Independent Programmable Center- or Left-aligned Output Waveform for Each Channel
̶ Independent Additional Edge Value for Each Channel, with Double Buffering, in Order to Generate
Additional Edges of the Output Waveform
̶ Independent Output Override for Each Channel
̶ Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned
Configuration or at Each Half-Period for Center-Aligned Configuration
̶ Independent Update Time Selection of Double Buffering Registers (Polarity, Duty Cycle and Additional
Edge Value) for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration, at
Each Half-Period for Center-Aligned Configuration
 2 2-bit Gray Up/Down Channels for Stepper Motor Control
 Spread Spectrum Counter to Allow a Constantly Varying Duty Cycle (only for Channel 0)
 Synchronous Channel Mode
̶ Synchronous Channels Share the Same Counter
̶ Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods
̶ Synchronous Channels Supports Connection of one Peripheral DMA Controller Channel (PDC or
DMA) Which Offers Buffer Transfer Without Processor Intervention To Update Duty-Cycle Registers
 2 Independent Events Lines Intended to Synchronize ADC Conversions
̶ Programmable delay for Events Lines to delay ADC measurements
 8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines and PDC or DMA Transfer
Requests
 8 Programmable Fault/Break Inputs Providing an Asynchronous Protection of PWM Outputs
̶ 1 User Driven through PIO Inputs
̶ PMC Driven when Crystal Oscillator Clock Fails
̶ ADC Controller Driven through Configurable Comparison Function
̶ Analog Comparator Controller Driven
̶ Timer/Counter Driven through Configurable Comparison Function
 Register Write Protection