SAM4E Series ARM-based Flash MCU DATASHEET Description The Atmel SAM4E series of Flash microcontrollers is based on the highperformance 32-bit ARM® Cortex®-M4 RISC processor and includes a floating point unit (FPU). It operates at a maximum speed of 120 MHz and features up to 1024 Kbytes of Flash, 2 Kbytes of cache memory and up to 128 Kbytes of SRAM. The SAM4E offers a rich set of advanced connectivity peripherals including 10/100 Mbps Ethernet MAC supporting IEEE 1588 and dual CAN.
1.
̶ Two CAN Controllers with eight Mailboxes ̶ 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control ̶ Real-time Event Management Cryptography ̶ AES 256-bit Key Algorithm compliant with FIPS Publication 197 Analog ̶ AFE (Analog Front End): 2x16-bit ADC, up to 24-channels, Differential Input Mode, Programmable Gain Stage, Auto Calibration and Automatic Offset Correction ̶ One 2-channel 12-bit 1 Msps DAC ̶ One Analog Comparator with
1.1 Configuration Summary The SAM4E series devices differ in memory size, package and features. Table 1-1 summarizes the configurations of the device family. Table 1-1. Configuration Summary Feature SAM4E16E Flash 1024 Kbytes SRAM SAM4E8C 512 Kbytes 1024 Kbytes 512 Kbytes 128 Kbytes 2 Kbytes 2 Kbytes LFBGA 144 TFBGA 100 Package LQFP 144 LQFP 100 Number of PIOs 117 79 External Bus Interface 8-bit Data, 4 Chip Selects, 24-bit Address - Up to 16 bits(1) Up to 16 bits(1) 16 ch.
Block Diagram IN Voltage Regulator PLL PMC Flash Unique Identifier JTAG & Serial Wire RC Osc 12/8/4 MHz In-circuit Emulator 24-bit Cortex-M4 Processor SysTick Counter N V Fmax 120 MHz I DSP C SUPC MPU FPU 3-20 MHz Osc SUPC WKUP0-WKUP15 Tamper Detection XIN32 XOUT32 Osc 32 kHz ERASE RC 32 kHz VDDIO 8 GPBREG VDDCORE RTT VDDPLL RTCOUT0 POR User Signature FLASH 1024 KB 512 KB SRAM 128 KB I D HCACHE HCACHE 7-layer AHB Bus Matrix Fmax 120 MHz DMAC USB 2.
PLL PMC Flash Unique Identifier JTAG & Serial Wire In-circuit Emulator XIN XOUT 24-bit Cortex-M4 Processor SysTick Counter N V Fmax 120 MHz I DSP C MPU FPU 3-20 MHz Osc WKUP0-WKUP15 SUPC XIN32 XOUT32 Osc 32 kHz ERASE RC 32 kHz VDDIO 8 GPBREG VDDCORE RTT VDDPLL RTCOUT0 POR User Signature FLASH 1024 KB 512 KB SRAM 128 KB 7-layer AHB Bus Matrix Fmax 120 MHz DMAC USB 2.
3. Signal Description Table 3-1 gives details on signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power – – 1.62V to 3.6V VDDIN Voltage Regulator Input, DAC and Analog Comparator Power Supply Power – – 1.62V to 3.6V(1) VDDOUT Voltage Regulator Output Power – – 1.2V Output VDDPLL Oscillator and PLL Power Supply Power – – 1.
Table 3-1.
Table 3-1.
Table 3-1.
4. Some PIO lines are shared with System I/Os. 4. Package and Pinout The SAM4E is available in TFBGA100, LFBGA144, LQFP100, and LQFP144 and packages described in the “SAM4E Mechanical Characteristics” section of this datasheet. 4.1 100-ball TFBGA Package and Pinout 4.1.1 100-ball TFBGA Package Outline The 100-ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Refer to Section 48.1 “100ball TFBGA Package Drawing” for details. 4.1.2 100-ball TFBGA Pinout Table 4-1.
4.2 144-ball LFBGA Package and Pinout 4.2.1 144-ball LFBGA Package Outline The 144-ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Refer to Section 48.2 “144ball LFBGA Package Drawing” for details. 4.2.2 144-ball LFBGA Pinout Table 4-2.
4.3 100-lead LQFP Package and Pinout 4.3.1 100-lead LQFP Package Outline The 100-lead LQFP package has a 0.5 mm ball pitch and respects Green Standards. Please refer to Section 48.3 “100-lead LQFP Package Drawing” for details. 4.3.2 100-lead LQFP Pinout Table 4-3.
4.4 144-lead LQFP Package and Pinout 4.4.1 144-lead LQFP Package Outline The 144-lead LQFP package has a 0.5 mm ball pitch and respects Green Standards. Please refer to Section 48.4 “144-lead LQFP Package Drawing” for details. 4.4.2 144-lead LQFP Pinout Table 4-4.
5. Power Considerations 5.1 Power Supplies The SAM4E has several types of power supply pins: 5.2 VDDCORE pins: power the core, the first flash rail, the embedded memories and the peripherals. Voltage ranges from 1.08V to 1.32V. VDDIO pins: power the peripheral I/O lines (Input/Output Buffers), the second flash rail, the backup part, the USB transceiver, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
Note: Restrictions: - For USB, VDDIO needs to be greater than 3.0V - For AFE, VDDIN needs to be greater than 2.4V - For DAC, VDDIN needs to be greater than 2.4V. Figure 5-2. Core Externally Supplied VDDIO Main Supply (1.62V-3.6V) USB Transceivers Can be the same supply ADC, DAC, Analog Comparator Supply (2.0V-3.6V) ADC, DAC Analog Comp. VDDIN VDDOUT VDDCORE Supply (1.08V-1.32V) Voltage Regulator VDDCORE VDDPLL Note: 5.4 Restrictions: - For USB, VDDIO needs to be greater than 3.
The Supply Controller, zero-power power-on reset, RTT, RTC, backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. The SAM4E can be awakened from this mode using the WKUP0-15 pins, the supply monitor (SM), the RTT or RTC wake-up event.
In both cases, depending on the value of the field Flash Low Power Mode (FLPM), the Flash enters three different modes: FLPM = 0 in Standby mode (Low consumption) FLPM = 1 in Deep power-down mode (Extra low consumption) FLPM = 2 in Idle mode. Memory ready for Read access Table 5-1 summarizes the power consumption, wake-up time and system state in wait mode. 5.5.3 Sleep Mode The purpose of sleep mode is to optimize power consumption of the device versus response time.
The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake-up sources can be individually configured. Table 5-1 below provides the configuration summary of the low-power modes. Table 5-1.
5.6 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-3.
5.7 Fast Start-up The SAM4E allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start-up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + RTC + RTT + USB). The fast restart circuitry, as shown in Figure 5-4, is fully asynchronous and provides a fast start-up signal to the Power Management Controller.
6. Input/Output Lines The SAM4E has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers.
6.2 System I/O Lines System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few. Described below in Table 6-1 are the SAM4E system I/O lines shared with PIO lines. These pins are software configurable as general purpose I/O or system pins. At start-up, the default function of these pins is always used. Table 6-1. System I/O Configuration Pin List.
7. Product Mapping Figure 7-1.
8. Memories 8.1 Embedded Memories 8.1.1 Internal SRAM The SAM4E device (1024 Kbytes) embeds a total of 128-Kbyte high-speed SRAM. The SRAM is accessible over System Cortex-M4 bus at address 0x2000_0000. The SRAM is in the bit band region. The bit band alias region is from 0x2200_0000 to 0x23FF_FFFF. 8.1.2 Internal ROM The SAM4E device embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA®), In Application Programming routines (IAP) and Fast Flash Programming Interface (FFPI).
Each Sector is organized in pages of 512 bytes. For sector 0: The smaller sector 0 has 16 pages of 512 bytes The smaller sector 1 has 16 pages of 512 bytes The larger sector has 96 pages of 512 bytes From Sector 1 to n: The rest of the array is composed of 64 Kbyte sector of each 128 pages of 512 bytes. Refer to Figure 8-2, "Flash Sector Organization" below. Figure 8-2.
̶ Erase pages (EPA) with FARG [1:0] = 0 to erase four pages or FARG [1:0] = 1 to erase eight pages. FARG [1:0] = 2 and FARG [1:0] = 3 must not be used.
erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted. The ERASE pin integrates a permanent pull-down. Consequently, it can be left unconnected during normal operation. However, it is recommended, in harsh environment, to connect it directly to GND if the erase operation is not used in the application. To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required.
The Flash of SAM4E is composed of 1024 Kbytes in a single bank. Table 8-2. 8.1.4 General-purpose Non-volatile Memory Bits GPNVMBit[#] Function 0 Security bit 1 Boot mode selection Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via GPNVM. A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
8.2 External Memories The SAM4E device features one External Bus Interface to provide an interface to a wide range of external memories and to any parallel peripheral. 8.3 Cortex-M Cache Controller (CMCC) The SAM4E device features one cache memory and his controller which improve code execution when the code runs out of Code section (memory from 0x0 to 0x2000_0000).
9. Real-time Event Management The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 9.1 Embedded Characteristics Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as AFEC or DACC, for example, to start measurement/conversion without processor intervention.
9.2 Real-time Event Mapping List Table 9-1. Real-time Event Mapping List Event Generator Event Manager Function IO (WKUP0/1) General Purpose Backup Register (GPBR) Security / Immediate GPBR clear (asynchronous) on Tamper detection through WKUP0/1 IO pins.
10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. See the system controller block diagram in Figure 10-1 on page 34.
Figure 10-1.
10.2 Power-on-Reset, Brownout and Supply Monitor The SAM4E device embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 10.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to the “Electrical Characteristics” section of the datasheet.
Programmable Schmitt trigger inputs Parallel capture mode: ̶ 36 ̶ Can be used to interface a CMOS digital image sensor (f.ex.
11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM4E device. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 11-1.
Table 11-1.
11.2 Peripheral Signal Multiplexing on I/O Lines The SAM4E device features five PIO Controllers on 144-pin versions (PIOA, PIOB, PIOC, PIOD and PIOE) that multiplex the I/O lines of the peripheral set. The SAM4E PIO Controllers control up to 32 lines. Each line can be assigned to one of three peripheral functions: A, B or C. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO Controllers.
11.2.1 PIO Controller A Multiplexing Table 11-2.
11.2.2 PIO Controller B Multiplexing Table 11-3.
11.2.3 PIO Controller C Multiplexing Table 11-4.
11.2.4 PIO Controller D Multiplexing Table 11-5.
11.2.5 PIO Controller E Multiplexing Table 11-6.
12. ARM Cortex-M4 Processor 12.1 Description The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be patched if a small programmable memory, for example flash, is available in the device.
12.4 Cortex-M4 Models 12.4.1 Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 12.4.1.1 Processor Modes and Privilege Levels for Software Execution The processor modes are: Thread mode Used to execute application software. The processor enters the Thread mode when it comes out of reset.
12.4.1.3 Core Registers Figure 12-2. Processor Core Registers R0 R1 R2 Low registers R3 R4 R5 General-purpose registers R6 R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL Table 12-2.
12.4.1.4 General-purpose Registers R0–R12 are 32-bit general-purpose registers for data operations. 12.4.1.5 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the Control Register indicates the stack pointer to use: 0 = Main Stack Pointer (MSP). This is the reset value. 1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. 12.4.1.6 Link Register The Link Register (LR) is register R14.
12.4.1.8 Program Status Register Name: PSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 29 C 28 V 27 Q 26 23 22 21 20 25 24 T 19 18 17 16 12 11 10 9 – 8 ISR_NUMBER 4 3 2 1 0 ICI/IT – 15 14 13 ICI/IT 7 6 5 ISR_NUMBER The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR.
12.4.1.9 Application Program Status Register Name: APSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 23 22 29 C 28 V 27 Q 26 21 20 19 18 – 15 14 25 – 24 17 16 GE[3:0] 13 12 11 10 9 8 3 2 1 0 – 7 6 5 4 – The APSR contains the current state of the condition flags from previous instruction executions. N: Negative Flag 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than.
12.4.1.10 Interrupt Program Status Register Name: IPSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 – 23 22 21 20 – 15 14 13 12 – 11 10 9 8 ISR_NUMBER 7 6 5 4 3 2 1 0 ISR_NUMBER The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
12.4.1.11 Execution Program Status Register Name: EPSR Access: Read/Write Reset: 0x000000000 31 23 30 22 29 – 28 21 20 27 26 25 24 T 16 ICI/IT 19 18 17 11 10 9 – 15 14 13 12 ICI/IT 7 6 5 8 – 4 3 2 1 0 – The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
12.4.1.12 Exception Mask Registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information.
12.4.1.13 Priority Mask Register Name: PRIMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRIMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The PRIMASK register prevents the activation of all exceptions with a configurable priority. PRIMASK 0: No effect 1: Prevents the activation of all exceptions with a configurable priority.
12.4.1.14 Fault Mask Register Name: FAULTMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FAULTMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK 0: No effect. 1: Prevents the activation of all exceptions except for NMI.
12.4.1.15 Base Priority Mask Register Name: BASEPRI Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 BASEPRI The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.
12.4.1.16 Control Register Name: CONTROL Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 FPCA 1 SPSEL 0 nPRIV – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread mode and indicates whether the FPU state is active.
Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See “ISB” .
12.4.1.17 Exceptions and Interrupts The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and “Exception Return” for more information. The NVIC registers control interrupt handling.
12.4.2 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. Figure 12-3. Memory Map 0xFFFFFFFF Vendor-specific 511 MB memory Private peripheral 1.0 MB bus External device 0xE0100000 0xE00FFFFF 0xE000 0000 0x DFFFFFFF 1.0 GB 0xA0000000 0x9FFFFFFF External RAM 0x43FFFFFF 1.
Memory Types Normal The processor can re-order transactions for efficiency, or perform speculative reads. Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. Strongly-ordered The processor preserves transaction order relative to all other transactions.
12.4.2.3 Behavior of Memory Accesses The following table describes the behavior of accesses to each region in the memory map. Table 12-4. Memory Access Behavior Address Range Memory Region Memory Type XN 0x00000000–0x1FFFFFFF Code Normal(1) – Executable region for program code. Data can also be put here. 0x20000000–0x3FFFFFFF SRAM Normal (1) – Executable region for data. Code can also be put here. This region includes bit band and bit band alias areas, see Table 12-6.
Instruction Prefetch and Branch Prediction The Cortex-M4 processor: Prefetches instructions ahead of execution Speculatively prefetches from branch target addresses. 12.4.2.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because: The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence.
Table 12-7. Peripheral Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses 0x40000000–0x400FFFFF Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit-addressable through bit-band alias. 0x42000000–0x43FFFFFF Peripheral bit-band region Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted.
Figure 12-4.
Figure 12-5. Little-endian Format Memory 7 Register 0 31 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte 12.4.2.7 Synchronization Primitives The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a LoadExclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory locations addressed by exclusive accesses by each processor. The processor removes its exclusive access tag if: It executes a CLREX instruction It executes a Store-Exclusive instruction, regardless of whether the write succeeds. An exception occurs.
Active An exception is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. Active and Pending The exception is being serviced by the processor and there is a pending exception from the same source. 12.4.3.2 Exception Types The exception types are: Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception.
SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. PendSV PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. SysTick A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception.
For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” . 12.4.3.3 Exception Handlers The processor handles exceptions using: Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ46 are the exceptions handled by ISRs. Fault Handlers Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers.
On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the SCB_VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, see “Vector Table Offset Register” . 12.4.3.5 Exception Priorities As Table 12-9 shows, all exceptions have an associated priority, with: A lower priority value indicating a higher priority Configurable priorities for all exceptions except Reset, Hard fault and NMI.
The completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” for more information. Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler.
Figure 12-7. Exception Stack Frame ... {aligner} FPSCR S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack Decreasing memory address IRQ top of stack Exception frame with floating-point storage ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Exception frame without floating-point storage Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. Table 12-10 shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one.
12.4.3.8 Fault Handling Faults are a subset of the exceptions, see “Exception Model” . The following generate a fault: A bus error on: ̶ An instruction fetch or vector table load ̶ A data access An internally-detected error such as an undefined instruction An attempt to execute an instruction from a memory region marked as Non-Executable (XN). A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
Fault Escalation and Hard Faults All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers” . The software can disable the execution of the handlers for these faults, see “System Handler Control and State Register” .
12.5 Power Management The Cortex-M4 processor sleep modes reduce the power consumption: Sleep mode stops the processor clock Deep sleep mode stops the system clock and switches off the PLL and flash memory. The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” . This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 12.5.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause an exception entry. For more information about the SCR, see “System Control Register” . 12.5.2.3 External Event Input The processor provides an external event input signal.
12.6 Cortex-M4 Instruction Set 12.6.1 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions. Angle brackets, <>, enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix.
Table 12-13.
Table 12-13.
Table 12-13.
Table 12-13.
Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags VCVT.S32.F32 Sd, Sm Convert between floating-point and integer – VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point – VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding – VCVT.F32.F16 Sd, Sm Converts half-precision value to single-precision – VCVTT.F32.F16 Sd, Sm Converts single-precision register to half-precision – VDIV.
12.6.2 CMSIS Functions ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, the user might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access: Table 12-14.
12.6.3 Instruction Descriptions 12.6.3.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” . 12.6.3.
ASR #n arithmetic shift right n bits, 1 ≤ n ≤ 32. LSL #n logical shift left n bits, 1 ≤ n ≤ 31. LSR #n logical shift right n bits, 1 ≤ n ≤ 32. ROR #n rotate right n bits, 1 ≤ n ≤ 31. RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm. If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction.
LSR Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the righthand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 12-9. The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer.
If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm. ROR with shift length, n, more than 32 is the same as ROR with shift length n-32. Figure 12-11. ROR #3 &DUU\ )ODJ RRX Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into bit[31] of the result. See Figure 12-12.
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes. For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned. Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number]. 12.6.3.
If adding two positive values results in a negative value If subtracting a positive value from a negative value generates a positive value If subtracting a negative value from a positive value generates a negative value. The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is discarded. See the instruction descriptions for more information. Note: Most instructions update the status flags only if the S suffix is specified.
Compare and Update Value The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3. CMP R0, R1 ; Compare R0 and R1, setting flags ITT GT ; IT instruction for the two GT conditions CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags MOVGT R4, R5 ; If still 'greater than', do R4 = R5 12.6.3.
12.6.4 Memory Access Instructions The table below shows the memory access instructions. Table 12-17.
12.6.4.1 ADR Load PC-relative address. Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. label is a PC-relative expression. See “PC-relative Expressions” . Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative.
12.6.4.2 LDR and STR, Immediate Offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
Pre-indexed Addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! Post-indexed Addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn.
Examples LDR LDRNE R8, [R10] R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 ; ; ; ; ; ; ; ; ; ; ; ; ; ; Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095.
Rm must not be SP and must not be PC Rt can be SP only for word loads and word stores Rt can be PC only for word loads. When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags.
12.6.4.4 LDR and STR, Unprivileged Load and Store with unprivileged access. Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word.
12.6.4.5 LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rt2 is the second register to load or store.
When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags.
highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist.
12.6.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional Execution” . reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.
12.6.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based.
MOV LDREX CMP ITT STREXEQ CMPEQ BNE .... R1, R0, R0, EQ R0, R0, try #0x1 [LockAddr] #0 R1, [LockAddr] #0 ; ; ; ; ; ; ; ; Initialize the ‘lock taken’ value try Load the lock value Is the lock free? IT instruction for STREXEQ and CMPEQ Try and claim the lock Did this succeed? No – try again Yes – we have the lock 12.6.4.9 CLREX Clear Exclusive. Syntax CLREX{cond} where: cond is an optional condition code, see “Conditional Execution” .
12.6.5 General Data Processing Instructions The table below shows the data processing instructions. Table 12-20.
Table 12-20.
12.6.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. ADC Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” .
̶ If the instruction is conditional, it must be the last instruction in the IT block With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: ̶ The user must not specify the S suffix ̶ The second operand must be a constant in the range 0 to 4095.
12.6.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND logical AND. ORR logical OR, or bit set. EOR logical Exclusive OR. BIC logical AND NOT, or bit clear. ORN logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” .
Examples AND ORREQ ANDS EORS BIC ORN ORNS 112 R9, R2, #0xFF00 R2, R0, R5 R9, R8, #0x19 R7, R11, #0x18181818 R0, R1, #0xab R7, R11, R14, ROR #4 R7, R11, R14, ASR #32 SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
12.6.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” .
12.6.5.4 CLZ Count Leading Zeros. Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the operand register. Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set and zero if bit[31] is set. Restrictions Do not use SP and do not use PC. Condition Flags This instruction does not change the flags.
12.6.5.5 CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional Execution” . Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options Operation These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not write the result to a register.
12.6.5.6 MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Operand2 is a flexible second operand.
Condition Flags If S is specified, these instructions: Update the N and Z flags according to the result Can update the C flag during the calculation of Operand2, see “Flexible Second Operand” Do not affect the V flag.
12.6.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the operand.
12.6.5.9 SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SADD16 Performs two 16-bit signed integer additions. SADD8 Performs four 8-bit signed integer additions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand.
12.6.5.10 SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHADD16 Signed Halving Add 16. SHADD8 Signed Halving Add 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register.
12.6.5.11 SHASX and SHSAX Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is any of: SHASX Add and Subtract with Exchange and Halving. SHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SHASX instruction: 1.
12.6.5.12 SHSUB16 and SHSUB8 Signed Halving Subtract 16 and Signed Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHSUB16 Signed Halving Subtract 16. SHSUB8 Signed Halving Subtract 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register.
12.6.5.13 SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SSUB16 Performs two 16-bit signed integer subtractions. SSUB8 Performs four 8-bit signed integer subtractions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to change endianness of data: The SSUB16 instruction: 1.
12.6.5.14 SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn where: op is any of: SASX Signed Add and Subtract with Exchange. SSAX Signed Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SASX instruction: 1.
12.6.5.15 TST and TEQ Test bits and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where cond is an optional condition code, see “Conditional Execution” . Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options Operation These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register.
12.6.5.16 UADD16 and UADD8 Unsigned Add 16 and Unsigned Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UADD16 Performs two 16-bit unsigned integer additions. UADD8 Performs four 8-bit unsigned integer additions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand.
12.6.5.17 UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UASX Add and Subtract with Exchange. USAX Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UASX instruction: 1.
12.6.5.18 UHADD16 and UHADD8 Unsigned Halving Add 16 and Unsigned Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHADD16 Unsigned Halving Add 16. UHADD8 Unsigned Halving Add 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the first operand. Rm is the register holding the second operand.
12.6.5.19 UHASX and UHSAX Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UHASX Add and Subtract with Exchange and Halving. UHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UHASX instruction: 1.
12.6.5.20 UHSUB16 and UHSUB8 Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHSUB16 Performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
12.6.5.21 SEL Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. Syntax SEL{}{} {,} , where: c, q are standard assembler syntax fields. Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation The SEL instruction: 1. Reads the value of each bit of APSR.GE. 2. Depending on the value of APSR.
12.6.5.22 USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation The USAD8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the absolute values of the differences together. 3.
12.6.5.23 USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Ra is the register that contains the accumulation value. Operation The USADA8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2.
12.6.5.24 USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where op is any of: USUB16 Unsigned Subtract 16. USUB8 Unsigned Subtract 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register: The USUB16 instruction: 1.
12.6.6 Multiply and Divide Instructions The table below shows the multiply and divide instructions. Table 12-21.
12.6.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional Execution” . S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” .
12.6.6.2 UMULL, UMAAL, UMLAL Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMAAL Unsigned Long Multiply with Accumulate Accumulate. UMLAL Unsigned Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold the accumulating value.
12.6.6.3 SMLA and SMLAW Signed Multiply Accumulate (halfwords). Syntax op{XY}{cond} Rd, Rn, Rm op{Y}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLA Signed Multiply Accumulate Long (halfwords). X and Y specifies which half of the source registers Rn and Rm are used as the first and second multiply operand. If X is B, then the bottom halfword, bits [15:0], of Rn is used. If X is T, then the top halfword, bits [31:16], of Rn is used. If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
Examples SMLABB SMLATB SMLATT SMLABT SMLABT SMLAWB SMLAWT R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R5, R6, R4, R1 ; ; R4, R3, R2 ; ; R10, R2, R5, R3 ; ; R10, R2, R1, R5 ; ; Multiplies bottom halfwords of R6 and R4, adds R1 and writes to R5 Multiplies top halfword of R6 with bottom halfword of R4, adds R1 and writes to R5 Multiplies top halfwords of R6 and R4, adds R1 and writes the sum to R5 Multiplies bottom halfword of R6 with top halfword of R4, adds R1 and writes to R5 Multiplies bott
12.6.6.4 SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra ; where: op is one of: SMLAD Signed Multiply Accumulate Dual. SMLADX Signed Multiply Accumulate Dual Reverse. X specifies which halfword of the source register Rn is used as the multiply operand. If X is omitted, the multiplications are bottom × bottom and top × top. If X is present, the multiplications are bottom × top and top × bottom. cond is an optional condition code, see “Conditional Execution” .
12.6.6.5 SMLAL and SMLALD Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long Dual. Syntax op{cond} RdLo, RdHi, Rn, Rm op{XY}{cond} RdLo, RdHi, Rn, Rm op{X}{cond} RdLo, RdHi, Rn, Rm where: op is one of: MLAL Signed Multiply Accumulate Long. SMLAL Signed Multiply Accumulate Long (halfwords, X and Y).
Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit product. Write the 64-bit product in RdLo and RdHi. Restrictions In these instructions: Do not use SP and do not use PC. RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags.
12.6.6.6 SMLSD and SMLSLD Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLSD Signed Multiply Subtract Dual. SMLSDX Signed Multiply Subtract Dual Reversed. SMLSLD Signed Multiply Subtract Long Dual. SMLSLDX Signed Multiply Subtract Long Dual Reversed. SMLAW Signed Multiply Accumulate (word by halfword). If X is present, the multiplications are bottom × top and top × bottom.
; ; SMLSDX R1, R3, R2, R0 ; ; ; ; SMLSLD R3, R6, R2, R7 ; ; ; ; SMLSLDX R3, R6, R2, R7 ; ; ; ; 144 with top halfword of R5, subtracts second from first, adds R6, writes to R0 Multiplies bottom halfword of R3 with top halfword of R2, multiplies top halfword of R3 with bottom halfword of R2, subtracts second from first, adds R0, writes to R1 Multiplies bottom halfword of R6 with bottom halfword of R2, multiplies top halfword of R6 with top halfword of R2, subtracts second from first, adds R6:R3, writes to R
12.6.6.7 SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract Syntax op{R}{cond} Rd, Rn, Rm, Ra where: op is one of: SMMLA Signed Most Significant Word Multiply Accumulate. SMMLS Signed Most Significant Word Multiply Subtract. If the X is omitted, the multiplications are bottom × bottom and top × top. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated.
SMMLS 146 R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits, ; subtracts R8, truncates and writes to R4.
12.6.6.8 SMMUL Signed Most Significant Word Multiply Syntax op{R}{cond} Rd, Rn, Rm where: op is one of: SMMUL Signed Most Significant Word Multiply. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the high word is extracted. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands.
12.6.6.9 SMUAD and SMUSD Signed Dual Multiply Add and Signed Dual Multiply Subtract Syntax op{X}{cond} Rd, Rn, Rm where: op is one of: SMUAD Signed Dual Multiply Add. SMUADX Signed Dual Multiply Add Reversed. SMUSD Signed Dual Multiply Subtract. SMUSDX Signed Dual Multiply Subtract Reversed. If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top. cond is an optional condition code, see “Conditional Execution” .
Examples SMUAD R0, R4, R5 SMUADX R3, R7, R4 SMUSD R3, R6, R2 SMUSDX R4, R5, R3 ; ; ; ; ; ; ; ; ; ; ; ; Multiplies bottom halfword of R4 with the bottom halfword of R5, adds multiplication of top halfword of R4 with top halfword of R5, writes to R0 Multiplies bottom halfword of R7 with top halfword of R4, adds multiplication of top halfword of R7 with bottom halfword of R4, writes to R3 Multiplies bottom halfword of R4 with bottom halfword of R6, subtracts multiplication of top halfword of R6 with t
12.6.6.10 SMUL and SMULW Signed Multiply (halfwords) and Signed Multiply (word by halfword) Syntax op{XY}{cond} Rd,Rn, Rm op{Y}{cond} Rd. Rn, Rm For SMULXY only: op is one of: SMUL{XY} Signed Multiply (halfwords). X and Y specify which halfword of the source registers Rn and Rm is used as the first and second multiply operand. If X is B, then the bottom halfword, bits [15:0] of Rn is used. If X is T, then the top halfword, bits [31:16] of Rn is used.
SMULWT R4, R5, R3 SMULWB R4, R5, R3 ; ; ; ; ; ; bottom halfword of R5, multiplies results and and writes to R0 Multiplies R5 with the top halfword of R3, extracts top 32 bits and writes to R4 Multiplies R5 with the bottom halfword of R3, extracts top 32 bits and writes to R4.
12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers.
12.6.6.12 SDIV and UDIV Signed Divide and Unsigned Divide. Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. Operation SDIV performs a signed integer division of the value in Rn by the value in Rm.
12.6.7 Saturating Instructions The table below shows the saturating instructions. Table 12-22.
12.6.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 31 for USAT.
12.6.7.2 SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm where: op is one of: SSAT16 Saturates a signed halfword value to a signed range. USAT16 Saturates a signed halfword value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 15 for USAT.
12.6.7.3 QADD and QSUB Saturating Add and Saturating Subtract, signed. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op is one of: QADD Saturating 32-bit add. QADD8 Saturating four 8-bit integer additions. QADD16 Saturating two 16-bit integer additions. QSUB Saturating 32-bit subtraction. QSUB8 Saturating four 8-bit integer subtraction. QSUB16 Saturating two 16-bit integer subtraction. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
Examples QADD16 158 R7, R4, R2 QADD8 R3, R1, R6 QSUB16 R4, R2, R3 QSUB8 R4, R2, R5 ; ; ; ; ; ; ; ; ; ; ; ; Adds halfwords of R4 with corresponding halfword of R2, saturates to 16 bits and writes to corresponding halfword of R7 Adds bytes of R1 to the corresponding bytes of R6, saturates to 8 bits and writes to corresponding byte of R3 Subtracts halfwords of R3 from corresponding halfword of R2, saturates to 16 bits, writes to corresponding halfword of R4 Subtracts bytes of R5 from the correspondin
12.6.7.4 QASX and QSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QASX Add and Subtract with Exchange and Saturate. QSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The QASX instruction: 1.
12.6.7.5 QDADD and QDSUB Saturating Double and Add and Saturating Double and Subtract, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QDADD Saturating Double and Add. QDSUB Saturating Double and Subtract. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm, Rn are registers holding the first and second operands. Operation The QDADD instruction: Doubles the second operand value.
12.6.7.6 UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned. Syntax op{cond} {Rd}, Rm, Rn where: type is one of: UQASX Add and Subtract with Exchange and Saturate. UQSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UQASX instruction: 1.
Examples UQASX R7, R4, R2 UQSAX R0, R3, R5 162 ; ; ; ; ; ; ; ; Adds top halfword of R4 with bottom halfword of R2, saturates to 16 bits, writes to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4, saturates to 16 bits, writes to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3, saturates to 16 bits, writes to top halfword of R0 Adds bottom halfword of R4 to top halfword of R5 saturates to 16 bits, writes to bottom halfword of R0.
12.6.7.7 UQADD and UQSUB Saturating Add and Saturating Subtract Unsigned. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op is one of: UQADD8 Saturating four unsigned 8-bit integer additions. UQADD16 Saturating two unsigned 16-bit integer additions. UDSUB8 Saturating four unsigned 8-bit integer subtractions. UQSUB16 Saturating two unsigned 16-bit integer subtractions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
UQSUB8 R1, R5, R6 ; halfword in R6 ; Subtracts bytes in R6 from corresponding byte of R5, ; saturates to 8 bits, writes to corresponding byte of R1. 12.6.8 Packing and Unpacking Instructions The table below shows the instructions that operate on packing and unpacking data. Table 12-23.
12.6.8.1 PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm} op{cond} {Rd}, Rn, Rm {, ASR #imm} where: op is one of: PKHBT Pack Halfword, bottom and top with shift. PKHTB Pack Halfword, top and bottom with shift. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register Rm is the second operand register holding the value to be optionally shifted. imm is the shift length.
12.6.8.2 SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd,} Rm {, ROR #n} op{cond} {Rd}, Rm {, ROR #n} where: op is one of: SXTB Sign extends an 8-bit value to a 32-bit value. SXTH Sign extends a 16-bit value to a 32-bit value. SXTB16 Sign extends two 8-bit values to two 16-bit values. UXTB Zero extends an 8-bit value to a 32-bit value. UXTH Zero extends a 16-bit value to a 32-bit value. UXTB16 Zero extends two 8-bit values to two 16-bit values.
12.6.8.3 SXTA and UXTA Signed and Unsigned Extend and Add Syntax op{cond} {Rd,} Rn, Rm {, ROR #n} op{cond} {Rd,} Rn, Rm {, ROR #n} where: op is one of: SXTAB Sign extends an 8-bit value to a 32-bit value and add. SXTAH Sign extends a 16-bit value to a 32-bit value and add. SXTAB16 Sign extends two 8-bit values to two 16-bit values and add. UXTAB Zero extends an 8-bit value to a 32-bit value and add. UXTAH Zero extends a 16-bit value to a 32-bit value and add.
Examples SXTAH UXTAB R4, R8, R6, ROR #16 ; ; ; R3, R4, R10 ; ; Rotates R6 right by 16 bits, obtains bottom halfword, sign extends to 32 bits, adds R8,and writes to R4 Extracts bottom byte of R10 and zero extends to 32 bits, adds R4, and writes to R3. 12.6.9 Bitfield Instructions The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields. Table 12-24.
12.6.9.1 BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb. Operation BFC clears a bitfield in a register.
12.6.9.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb.
12.6.9.3 SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits.
12.6.10 Branch and Control Instructions The table below shows the branch and control instructions. Table 12-25.
12.6.10.1 B, BL, BX, and BLX Branch instructions. Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional Execution” . label is a PC-relative expression. See “PC-relative Expressions” . Rm is a register that indicates an address to branch to.
Condition Flags These instructions do not change the flags. Examples 174 B BLE B.W BEQ BEQ.
12.6.10.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions.
12.6.10.3 IT If-Then condition instruction. Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then.
All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one Each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block. Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them.
12.6.10.4 TBB and TBH Table Branch Byte and Table Branch Halfword. Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. Rm is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table.
; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 179
12.6.11 Floating-point Instructions The table below shows the floating-point instructions. These instructions are only available if the FPU is included, and enabled, in the system. See “Enabling the FPU” for information about enabling the floating-point unit. Table 12-27.
Table 12-27.
12.6.11.1 VABS Floating-point Absolute. Syntax VABS{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd, Sm are the destination floating-point value and the operand floating-point value. Operation This instruction: 1. Takes the absolute value of the operand floating-point register. 2. Places the results in the destination floating-point register. Restrictions There are no restrictions. Condition Flags The floating-point instruction clears the sign bit.
12.6.11.2 VADD Floating-point Add Syntax VADD{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd, is the destination floating-point value. Sn, Sm are the operand floating-point values. Operation This instruction: 1. Adds the values in the two floating-point operand registers. 2. Places the results in the destination floating-point register. Restrictions There are no restrictions. Condition Flags This instruction does not change the flags.
12.6.11.3 VCMP, VCMPE Compares two floating-point registers, or one floating-point register and zero. Syntax VCMP{E}{cond}.F32 Sd, Sm VCMP{E}{cond}.F32 Sd, #0.0 where: cond is an optional condition code, see “Conditional Execution” . E If present, any NaN operand causes an Invalid Operation exception. Otherwise, only a signaling NaN causes the exception. Sd is the floating-point operand to compare. Sm is the floating-point operand that is compared with. Operation This instruction: 1.
12.6.11.4 VCVT, VCVTR between Floating-point and Integer Converts a value in a register from floating-point to a 32-bit integer. Syntax VCVT{R}{cond}.Tm.F32 Sd, Sm VCVT{cond}.F32.Tm Sd, Sm where: R If R is specified, the operation uses the rounding mode specified by the FPSCR. If R is omitted. the operation uses the Round towards Zero rounding mode. cond is an optional condition code, see “Conditional Execution” . Tm is the data type for the operand.
12.6.11.5 VCVT between Floating-point and Fixed-point Converts a value in a register from floating-point to and from fixed-point. Syntax VCVT{cond}.Td.F32 Sd, Sd, #fbits VCVT{cond}.F32.Td Sd, Sd, #fbits where: cond is an optional condition code, see “Conditional Execution” . Td is the data type for the fixed-point number. It must be one of: S16 U16 signed 16-bit value. unsigned 16-bit value. S32 U32 signed 32-bit value. unsigned 32-bit value.
12.6.11.6 VCVTB, VCVTT Converts between a half-precision value and a single-precision value. Syntax VCVT{y}{cond}.F32.F16 Sd, Sm VCVT{y}{cond}.F16.F32 Sd, Sm where: y Specifies which half of the operand register Sm or destination register Sd is used for the operand or destination: - If y is B, then the bottom half, bits [15:0], of Sm or Sd is used. - If y is T, then the top half, bits [31:16], of Sm or Sd is used. cond is an optional condition code, see “Conditional Execution” .
12.6.11.7 VDIV Divides floating-point values. Syntax VDIV{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination register. Sn, Sm are the operand registers. Operation This instruction: 1. Divides one floating-point value by another floating-point value. 2. Writes the result to the floating-point destination register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags.
12.6.11.8 VFMA, VFMS Floating-point Fused Multiply Accumulate and Subtract. Syntax VFMA{cond}.F32 {Sd,} Sn, Sm VFMS{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination register. Sn, Sm are the operand registers. Operation The VFMA instruction: 1. Multiplies the floating-point values in the operand registers. 2. Accumulates the results into the destination register. The result of the multiply is not rounded before the accumulation.
12.6.11.9 VFNMA, VFNMS Floating-point Fused Negate Multiply Accumulate and Subtract. Syntax VFNMA{cond}.F32 {Sd,} Sn, Sm VFNMS{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination register. Sn, Sm are the operand registers. Operation The VFNMA instruction: 1. Negates the first floating-point operand register. 2. Multiplies the first floating-point operand with second floating-point operand. 3.
12.6.11.10 VLDM Floating-point Load Multiple Syntax VLDM{mode}{cond}{.size} Rn{!}, list where: mode is the addressing mode: - IA Increment After. The consecutive addresses start at the address speci fied in Rn. - DB Decrement Before. The consecutive addresses end just before the address specified in Rn. cond is an optional condition code, see “Conditional Execution” . size is an optional data size specifier. Rn is the base register.
12.6.11.11 VLDR Loads a single extension register from memory Syntax VLDR{cond}{.64} VLDR{cond}{.64} VLDR{cond}{.64} VLDR{cond}{.32} VLDR{cond}{.32} VLDR{cond}{.32} Dd, Dd, Dd, Sd, Sd, Sd, [Rn{#imm}] label [PC, #imm}] [Rn {, #imm}] label [PC, #imm] where: cond is an optional condition code, see “Conditional Execution” . 64, 32 are the optional data size specifiers. Dd is the destination register for a doubleword load. Sd is the destination register for a singleword load.
12.6.11.12 VLMA, VLMS Multiplies two floating-point values, and accumulates or subtracts the results. Syntax VLMA{cond}.F32 Sd, Sn, Sm VLMS{cond}.F32 Sd, Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination floating-point value. Sn, Sm are the operand floating-point values. Operation The floating-point Multiply Accumulate instruction: 1. Multiplies two floating-point values. 2. Adds the results to the destination floating-point value.
12.6.11.13 VMOV Immediate Move floating-point Immediate Syntax VMOV{cond}.F32 Sd, #imm where: cond is an optional condition code, see “Conditional Execution” . Sd is the branch destination. imm is a floating-point constant. Operation This instruction copies a constant value to a floating-point register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags.
12.6.11.14 VMOV Register Copies the contents of one register to another. Syntax VMOV{cond}.F64 Dd, Dm VMOV{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution” . Dd is the destination register, for a doubleword operation. Dm is the source register, for a doubleword operation. Sd is the destination register, for a singleword operation. Sm is the source register, for a singleword operation.
12.6.11.15 VMOV Scalar to ARM Core Register Transfers one word of a doubleword floating-point register to an ARM core register. Syntax VMOV{cond} Rt, Dn[x] where: cond is an optional condition code, see “Conditional Execution” . Rt is the destination ARM core register. Dn is the 64-bit doubleword register. x Specifies which half of the doubleword register to use: - If x is 0, use lower half of doubleword register - If x is 1, use upper half of doubleword register.
12.6.11.16 VMOV ARM Core Register to Single Precision Transfers a single-precision register to and from an ARM core register. Syntax VMOV{cond} Sn, Rt VMOV{cond} Rt, Sn where: cond is an optional condition code, see “Conditional Execution” . Sn is the single-precision floating-point register. Rt is the ARM core register. Operation This instruction transfers: The contents of a single-precision register to an ARM core register.
12.6.11.17 VMOV Two ARM Core Registers to Two Single Precision Transfers two consecutively numbered single-precision registers to and from two ARM core registers. Syntax VMOV{cond} Sm, Sm1, Rt, Rt2 VMOV{cond} Rt, Rt2, Sm, Sm where: cond is an optional condition code, see “Conditional Execution” . Sm is the first single-precision register. Sm1 is the second single-precision register. This is the next single-precision register after Sm. Rt is the ARM core register that Sm is transferred to or from.
12.6.11.18 VMOV ARM Core Register to Scalar Transfers one word to a floating-point register from an ARM core register. Syntax VMOV{cond}{.32} Dd[x], Rt where: cond is an optional condition code, see “Conditional Execution” . 32 is an optional data size specifier. Dd[x] is the destination, where [x] defines which half of the doubleword is transferred, as follows: If x is 0, the lower half is extracted If x is 1, the upper half is extracted. Rt is the source ARM core register.
12.6.11.19 VMRS Move to ARM Core register from floating-point System Register. Syntax VMRS{cond} Rt, FPSCR VMRS{cond} APSR_nzcv, FPSCR where: cond is an optional condition code, see “Conditional Execution” . Rt is the destination ARM core register. This register can be R0–R14. APSR_nzcv Transfer floating-point flags to the APSR flags. Operation This instruction performs one of the following actions: Copies the value of the FPSCR to a general-purpose register.
12.6.11.20 VMSR Move to floating-point System Register from ARM Core register. Syntax VMSR{cond} FPSCR, Rt where: cond is an optional condition code, see “Conditional Execution” . Rt is the general-purpose register to be transferred to the FPSCR. Operation This instruction moves the value of a general-purpose register to the FPSCR. See “Floating-point Status Control Register” for more information. Restrictions The restrictions are: Rt cannot be PC or SP.
12.6.11.21 VMUL Floating-point Multiply. Syntax VMUL{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination floating-point value. Sn, Sm are the operand floating-point values. Operation This instruction: 1. Multiplies two floating-point values. 2. Places the results in the destination register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags.
12.6.11.22 VNEG Floating-point Negate. Syntax VNEG{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination floating-point value. Sm is the operand floating-point value. Operation This instruction: 1. Negates a floating-point value. 2. Places the results in a second floating-point register. The floating-point instruction inverts the sign bit. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags.
12.6.11.23 VNMLA, VNMLS, VNMUL Floating-point multiply with negation followed by add or subtract. Syntax VNMLA{cond}.F32 Sd, Sn, Sm VNMLS{cond}.F32 Sd, Sn, Sm VNMUL{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination floating-point register. Sn, Sm are the operand floating-point registers. Operation The VNMLA instruction: 1. Multiplies two floating-point register values. 2.
12.6.11.24 VPOP Floating-point extension register Pop. Syntax VPOP{cond}{.size} list where: cond is an optional condition code, see “Conditional Execution” . size is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list. list is the list of extension registers to be loaded, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets.
12.6.11.25 VPUSH Floating-point extension register Push. Syntax VPUSH{cond}{.size} list where: cond is an optional condition code, see “Conditional Execution” . size is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list. list is a list of the extension registers to be stored, as a list of consecutively num bered doubleword or singleword registers, separated by commas and sur rounded by brackets.
12.6.11.26 VSQRT Floating-point Square Root. Syntax VSQRT{cond}.F32 Sd, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination floating-point value. Sm is the operand floating-point value. Operation This instruction: Calculates the square root of the value in a floating-point register. Writes the result to another floating-point register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags.
12.6.11.27 VSTM Floating-point Store Multiple. Syntax VSTM{mode}{cond}{.size} Rn{!}, list where: mode is the addressing mode: - IA Increment After. The consecutive addresses start at the address speci fied in Rn. This is the default and can be omitted. - DB Decrement Before. The consecutive addresses end just before the address specified in Rn. cond is an optional condition code, see “Conditional Execution” . size is an optional data size specifier.
12.6.11.28 VSTR Floating-point Store. Syntax VSTR{cond}{.32} Sd, [Rn{, #imm}] VSTR{cond}{.64} Dd, [Rn{, #imm}] where cond is an optional condition code, see “Conditional Execution” . 32, 64 are the optional data size specifiers. Sd is the source register for a singleword store. Dd is the source register for a doubleword store. Rn is the base register. The SP can be used. imm is the + or - immediate offset used to form the address. Values are multiples of 4 in the range 0–1020.
12.6.11.29 VSUB Floating-point Subtract. Syntax VSUB{cond}.F32 {Sd,} Sn, Sm where: cond is an optional condition code, see “Conditional Execution” . Sd is the destination floating-point value. Sn, Sm are the operand floating-point value. Operation This instruction: 1. Subtracts one floating-point value from another floating-point value. 2. Places the results in the destination floating-point register. Restrictions There are no restrictions. Condition Flags These instructions do not change the flags.
12.6.12 Miscellaneous Instructions The table below shows the remaining Cortex-M4 instructions. Table 12-28.
12.6.12.1 BKPT Breakpoint. Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0–255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
Condition Flags This instruction does not change the condition flags. Examples CPSID CPSID CPSIE CPSIE i f i f ; ; ; ; Disable interrupts and configurable fault handlers (set PRIMASK) Disable interrupts and all fault handlers (set FAULTMASK) Enable interrupts and configurable fault handlers (clear PRIMASK) Enable interrupts and fault handlers (clear FAULTMASK) 12.6.12.3 DMB Data Memory Barrier. Syntax DMB{cond} where: cond is an optional condition code, see “Conditional Execution” .
12.6.12.4 DSB Data Synchronization Barrier. Syntax DSB{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. Condition Flags This instruction does not change the flags. Examples DSB ; Data Synchronization Barrier 12.6.12.
12.6.12.6 MRS Move the contents of a special register to a general-purpose register. Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag.
Operation The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR. See “Application Program Status Register” . Privileged software can access all special registers. In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
12.6.12.9 SEV Send Event. Syntax SEV{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see “Power Management” . Condition Flags This instruction does not change the flags. Examples SEV ; Send Event 12.6.12.10 SVC Supervisor Call.
12.6.12.11 WFE Wait For Event. Syntax WFE{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation WFE is a hint instruction.
12.7 Cortex-M4 Core Peripherals 12.7.1 Peripherals Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. See Section 12.8 ”Nested Vectored Interrupt Controller (NVIC)” System Control Block (SCB) The System Control Block (SCB) is the programmers model interface to the processor.
12.8 Nested Vectored Interrupt Controller (NVIC) This section describes the NVIC and the registers it uses. The NVIC supports: Up to 47 interrupts. A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. Level detection of interrupt signals. Dynamic reprioritization of interrupts. Grouping of priority values into group priority and subpriority fields. Interrupt tail-chaining.
Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector table are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the “Vector Table Offset Register” . 12.8.2.1 NVIC Programming Hints The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts.
Note: 222 1. Each array element corresponds to a single NVIC register, for example the ICER[0] element corresponds to the ICER0.
12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface Table 12-32. Nested Vectored Interrupt Controller (NVIC) Register Mapping Offset Register Name Access Reset 0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read/Write 0x00000000 0XE000E180 Interrupt Clear-enable Register 0 NVIC_ICER0 Read/Write 0x00000000 ... ... ... ... ...
12.8.3.1 Interrupt Set-enable Registers Name: NVIC_ISERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETENA 23 22 21 20 SETENA 15 14 13 12 SETENA 7 6 5 4 SETENA These registers enable interrupts and show which interrupts are enabled. SETENA: Interrupt Set-enable Write: 0: No effect. 1: Enables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled. Notes: 224 1.
12.8.3.2 Interrupt Clear-enable Registers Name: NVIC_ICERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA These registers disable interrupts, and show which interrupts are enabled. CLRENA: Interrupt Clear-enable Write: 0: No effect. 1: Disables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled.
12.8.3.3 Interrupt Set-pending Registers Name: NVIC_ISPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETPEND 23 22 21 20 SETPEND 15 14 13 12 SETPEND 7 6 5 4 SETPEND These registers force interrupts into the pending state, and show which interrupts are pending. SETPEND: Interrupt Set-pending Write: 0: No effect. 1: Changes the interrupt state to pending. Read: 0: Interrupt is not pending.
12.8.3.4 Interrupt Clear-pending Registers Name: NVIC_ICPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRPEND 23 22 21 20 CLRPEND 15 14 13 12 CLRPEND 7 6 5 4 CLRPEND These registers remove the pending state from interrupts, and show which interrupts are pending. CLRPEND: Interrupt Clear-pending Write: 0: No effect. 1: Removes the pending state from an interrupt. Read: 0: Interrupt is not pending.
12.8.3.5 Interrupt Active Bit Registers Name: NVIC_IABRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACTIVE 23 22 21 20 ACTIVE 15 14 13 12 ACTIVE 7 6 5 4 ACTIVE These registers indicate which interrupts are active. ACTIVE: Interrupt Active Flags 0: Interrupt is not active. 1: Interrupt is active. Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
12.8.3.6 Interrupt Priority Registers Name: NVIC_IPRx [x=0..12] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI3 23 22 21 20 PRI2 15 14 13 12 PRI1 7 6 5 4 PRI0 The NVIC_IPR0–NVIC_IPR12 registers provide a 8-bit priority field for each interrupt. These registers are byte-accessible. Each register holds four priority fields that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[46].
12.8.3.7 Software Trigger Interrupt Register Name: NVIC_STIR Access: Write-only Reset: 0x000000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INTID 7 6 5 4 3 2 1 0 INTID Write to this register to generate an interrupt from the software. INTID: Interrupt ID Interrupt ID of the interrupt to trigger, in the range 0–239. For example, a value of 0x03 specifies interrupt IRQ3.
12.9 System Control Block (SCB) The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions.
12.9.1 System Control Block (SCB) User Interface Table 12-33.
12.9.1.1 Auxiliary Control Register Name: SCB_ACTLR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 12 11 10 9 DISOOFP 8 DISFPCA 4 3 2 1 0 DISFOLD DISDEFWBUF DISMCYCINT – 23 22 21 20 – 15 14 13 – 7 6 5 – The SCB_ACTLR provides disable bits for the following processor functions: • IT folding • Write buffer use for accesses to the default memory map • Interruption of multi-cycle instructions.
12.9.1.2 CPUID Base Register Name: SCB_CPUID Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 19 18 25 24 17 16 Implementer 23 22 21 20 Variant 15 14 Constant 13 12 11 10 9 8 3 2 1 0 PartNo 7 6 5 4 PartNo Revision The SCB_CPUID register contains the processor part number, version, and implementation information. Implementer: Implementer Code 0x41: ARM. Variant: Variant Number It is the r value in the rnpn product revision identifier: 0x0: Revision 0.
12.9.1.
PENDSVCLR: PendSV Clear-pending Write: 0: No effect. 1: Removes the pending state from the PendSV exception. PENDSTSET: SysTick Exception Set-pending Write: 0: No effect. 1: Changes SysTick exception state to pending. Read: 0: SysTick exception is not pending. 1: SysTick exception is pending. PENDSTCLR: SysTick Exception Clear-pending Write: 0: No effect. 1: Removes the pending state from the SysTick exception. This bit is Write-only. On a register read, its value is Unknown.
12.9.1.4 Vector Table Offset Register Name: SCB_VTOR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 1 0 TBLOFF 23 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 TBLOFF 6 5 4 The SCB_VTOR indicates the offset of the vector table base address from memory address 0x00000000. TBLOFF: Vector Table Base Offset It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
12.9.1.5 Application Interrupt and Reset Control Register Name: SCB_AIRCR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 VECTKEYSTAT/VECTKEY 26 25 24 23 22 21 20 19 VECTKEYSTAT/VECTKEY 18 17 16 15 ENDIANNESS 14 13 9 PRIGROUP 8 7 6 12 11 10 4 3 2 – 5 – 1 VECTCLRACTI SYSRESETREQ VE 0 VECTRESET The SCB_AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system.
Interrupt Priority Level Value, PRI_N[7:0] PRIGROUP Binary Point 0b101 (1) Number of Group Priority Bits Subpriority Bits Group Priorities Subpriorities bxx.yyyyyy [7:6] [5:0] 4 64 0b110 bx.yyyyyyy [7] [6:0] 2 128 0b111 b.yyyyyyy None [7:0] 1 256 Note: 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Determining preemption of an exception uses only the group priority field.
12.9.1.6 System Control Register Name: SCB_SCR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 SLEEPDEEP 1 SLEEPONEXIT 0 – – 23 22 21 20 – 15 14 13 12 – 7 6 – 5 4 SEVONPEND SEVONPEND: Send Event on Pending Bit 0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
12.9.1.7 Configuration and Control Register Name: SCB_CCR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 12 11 10 9 STKALIGN 8 BFHFNMIGN 4 3 2 DIV_0_TRP UNALIGN_TRP – – 23 22 21 20 – 15 14 13 – 7 6 5 – 1 0 USERSETMPE NONBASETHR ND DENA The SCB_CCR controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore BusFaults.
If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. USERSETMPEND: Unprivileged Software Access Enables unprivileged software access to the NVIC_STIR, see “Software Trigger Interrupt Register” : 0: Disable. 1: Enable. NONBASETHRDENA: Thread Mode Enable Indicates how the processor enters Thread mode: 0: The processor can enter the Thread mode only when no exception is active.
12.9.1.8 System Handler Priority Registers The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. They are byte-accessible. The system fault handlers and the priority field and register for each handler are: Table 12-34.
12.9.1.9 System Handler Priority Register 1 Name: SCB_SHPR1 Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 PRI_6 15 14 13 12 PRI_5 7 6 5 4 PRI_4 PRI_6: Priority Priority of system handler 6, UsageFault. PRI_5: Priority Priority of system handler 5, BusFault. PRI_4: Priority Priority of system handler 4, MemManage.
12.9.1.10 System Handler Priority Register 2 Name: SCB_SHPR2 Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_11 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – PRI_11: Priority Priority of system handler 11, SVCall.
12.9.1.11 System Handler Priority Register 3 Name: SCB_SHPR3 Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_15 23 22 21 20 PRI_14 15 14 13 12 – 7 6 5 4 – PRI_15: Priority Priority of system handler 15, SysTick exception. PRI_14: Priority Priority of system handler 14, PendSV.
12.9.1.
MEMFAULTPENDED: Memory Management Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. USGFAULTPENDED: Usage Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. SYSTICKACT: SysTick Exception Active Read: 0: The exception is not active.
If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault. The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type.
12.9.1.13 Configurable Fault Status Register Name: SCB_CFSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 DIVBYZERO 24 UNALIGNED 21 20 19 NOCP 18 INVPC 17 INVSTATE 16 UNDEFINSTR 13 12 STKERR 11 UNSTKERR 10 IMPRECISERR 9 PRECISERR 8 IBUSERR 5 MLSPERR 4 MSTKERR 3 MUNSTKERR 2 – 1 DACCVIOL 0 IACCVIOL – 23 22 – 15 BFARVALID 14 7 MMARVALID 6 – – IACCVIOL: Instruction Access Violation Flag This is part of “MMFSR: Memory Management Fault Status Subregister” .
MLSPERR: MemManage during Lazy State Preservation This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: No MemManage fault occurred during the floating-point lazy state preservation. 1: A MemManage fault occurred during the floating-point lazy state preservation. MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: The value in SCB_MMFAR is not a valid fault address.
UNSTKERR: Bus Fault on Unstacking for a Return From Exception This is part of “BFSR: Bus Fault Status Subregister” . 0: No unstacking fault. 1: Unstack for an exception return has caused one or more bus faults. This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address to the BFAR.
INVPC: Invalid PC Load Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN: 0: No invalid PC load usage fault. 1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC.
12.9.1.14 Configurable Fault Status Register (Byte Access) Name: SCB_CFSR (BYTE) Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UFSR 23 22 21 20 UFSR 15 14 13 12 BFSR 7 6 5 4 MMFSR MMFSR: Memory Management Fault Status Subregister The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section 12.9.1.13.
12.9.1.15 Hard Fault Status Register Name: SCB_HFSR Access: Read/Write Reset: 0x000000000 31 DEBUGEVT 30 FORCED 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 VECTTBL 0 – – 20 – 15 14 13 12 – 7 6 5 4 – The SCB_HFSR gives information about events that activate the hard fault handler. This register is read, write to clear. This means that bits in the register read normally, but wrting a 1 to any bit clears that bit to 0.
12.9.1.16 MemManage Fault Address Register Name: SCB_MMFAR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_MMFAR contains the address of the location that generated a memory management fault.
12.9.1.17 Bus Fault Address Register Name: SCB_BFAR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_BFAR contains the address of the location that generated a bus fault. ADDRESS: Bus Fault Generation Location Address When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the bus fault.
12.10 System Timer (SysTick) The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the SYST_RVR on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging, the counter does not decrement. The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops.
12.10.1 System Timer (SysTick) User Interface Table 12-35.
12.10.1.1 SysTick Control and Status Name: SYST_CSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 COUNTFLAG 11 10 9 8 3 2 CLKSOURCE 1 TICKINT 0 ENABLE – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 The SysTick SYST_CSR enables the SysTick features. COUNTFLAG: Count Flag Returns 1 if the timer counted to 0 since the last time this was read. CLKSOURCE: Clock Source Indicates the clock source: 0: External Clock. 1: Processor Clock.
12.10.1.2 SysTick Reload Value Registers Name: SYST_RVR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 RELOAD 15 14 13 12 RELOAD 7 6 5 4 RELOAD The SYST_RVR specifies the start value to load into the SYST_CVR. RELOAD: SYST_CVR Load Value Value to load into the SYST_CVR when the counter is enabled and when it reaches 0. The RELOAD value can be any value in the range 0x00000001–0x00FFFFFF.
12.10.1.3 SysTick Current Value Register Name: SYST_CVR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT The SysTick SYST_CVR contains the current value of the SysTick counter. CURRENT: SysTick Counter Current Value Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
12.10.1.4 SysTick Calibration Value Register Name: SYST_CALIB Access: Read/Write Reset: 0x00003A98 31 NOREF 30 SKEW 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 20 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS The SysTick SYST_CSR indicates the SysTick calibration properties. NOREF: No Reference Clock It indicates whether the device provides a reference clock to the processor: 0: Reference clock provided. 1: No reference clock provided.
12.11 Memory Protection Unit (MPU) The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: Independent attribute settings for each region Overlapping regions Export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines: Eight separate memory regions, 0–7 A background region.
The table below shows the encodings for the TEX, C, B, and S access permission bits. Table 12-37. TEX C 0 TEX, C, B, and S Encoding B 0 1 S Memory Type Shareability Other Attributes x (1) Strongly-ordered Shareable – x (1) Device Shareable – Normal Not shareable 0 0 b000 1 Outer and inner write-through. No write allocate. Shareable 1 Not shareable 0 1 0 Normal 1 Shareable 0 Not shareable 0 Normal 1 x (1) Reserved encoding – 0 x (1) Implementation defined attributes.
Table 12-39 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 12-39.
STRH R2, [R0, #0x8] ; Region Size and Enable The software must use memory barrier instructions: Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings After the MPU setup, if it includes memory transfers that must use the new MPU settings.
STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable 12.11.1.5 Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” . The least significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion.
Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as follows: Table 12-40.
12.11.2 Memory Protection Unit (MPU) User Interface Table 12-41.
12.11.2.1 MPU Type Register Name: MPU_TYPE Access: Read/Write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEPARATE – 23 22 21 20 IREGION 15 14 13 12 DREGION 7 6 5 4 – The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. IREGION: Instruction Region Indicates the number of supported MPU instruction regions. Always contains 0x00.
12.11.2.2 MPU Control Register Name: MPU_CTRL Access: Read/Write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 PRIVDEFENA 1 HFNMIENA 0 ENABLE – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
When ENABLE and PRIVDEFENA are both set to 1: • For privileged accesses, the default memory map is as described in “Memory Model” . Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. • Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit.
12.11.2.3 MPU Region Number Register Name: MPU_RNR Access: Read/Write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 REGION The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASRs. REGION: MPU Region Referenced by the MPU_RBAR and MPU_RASRs Indicates the MPU region referenced by the MPU_RBAR and MPU_RASRs.
12.11.2.4 MPU Region Base Address Register Name: MPU_RBAR Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.5 MPU Region Attribute and Size Register Name: MPU_RASR Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.11.2.6 MPU Region Base Address Register Alias 1 Name: MPU_RBAR_A1 Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.7 MPU Region Attribute and Size Register Alias 1 Name: MPU_RASR_A1 Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.11.2.8 MPU Region Base Address Register Alias 2 Name: MPU_RBAR_A2 Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.9 MPU Region Attribute and Size Register Alias 2 Name: MPU_RASR_A2 Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.11.2.10 MPU Region Base Address Register Alias 3 Name: MPU_RBAR_A3 Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.11 MPU Region Attribute and Size Register Alias 3 Name: MPU_RASR_A3 Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.12 Floating Point Unit (FPU) The Cortex-M4F FPU implements the FPv4-SP floating-point extension. The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.
12.12.2 Floating Point Unit (FPU) User Interface Table 12-42.
12.12.2.1 Coprocessor Access Control Register Name: CPACR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 19 18 25 24 17 16 – 23 22 21 CP11 15 20 CP10 14 13 – 12 11 10 9 8 3 2 1 0 – 7 6 5 4 – The CPACR specifies the access privileges for coprocessors. CP10: Access Privileges for Coprocessor 10 The possible values of each field are: 0: Access denied. Any attempted access generates a NOCP UsageFault. 1: Privileged access only.
12.12.2.2 Floating-point Context Control Register Name: FPCCR Access: Read/Write Reset: 0x000000000 31 ASPEN 30 LSPEN 29 23 22 21 28 27 26 25 24 19 18 17 16 – 20 – 15 14 13 12 – 11 10 9 8 MONRDY 7 – 6 BFRDY 5 MMRDY 4 HFRDY 3 THREAD 2 – 1 USER 0 LSPACT The FPCCR sets or returns FPU control data. ASPEN: Automatic Hardware State Preservation And Restoration Enables CONTROL bit [2] setting on execution of a floating-point instruction.
HFRDY: Hard Fault Ready 0: The priority did not permit to set the HardFault handler to the pending state when the floating-point stack frame was allocated. 1: The priority permitted to set the HardFault handler to the pending state when the floating-point stack frame was allocated. THREAD: Thread Mode 0: The mode was not the Thread Mode when the floating-point stack frame was allocated. 1: The mode was the Thread Mode when the floating-point stack frame was allocated.
12.12.2.3 Floating-point Context Address Register Name: FPCAR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 ADDRESS 4 The FPCAR holds the location of the unpopulated floating-point register space allocated on an exception stack frame.
12.12.2.4 Floating-point Status Control Register Name: FPSCR Access: Read/Write Reset: 0x000000000 31 N 23 30 Z 29 C 28 V 27 – 26 AHP 25 DN 24 FZ 22 21 20 19 18 17 16 11 10 9 8 3 UFC 2 OFC 1 DZC 0 IOC RMode 15 – 14 13 12 – 7 IDC 6 5 – 4 IXC The FPSCR provides all necessary User level control of the floating-point system. N: Negative Condition Code Flag Floating-point comparison operations update this flag.
0b10: Round towards Minus Infinity (RM) mode. 0b11: Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions. IDC: Input Denormal Cumulative Exception IDC is a cumulative exception bit for floating-point exception; see also bits [4:0]. This bit is set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it.
12.12.2.5 Floating-point Default Status Control Register Name: FPDSCR Access: Read/Write Reset: 0x000000000 31 23 30 29 – 28 27 26 AHP 25 DN 24 FZ 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 RMode 15 – 14 13 12 – 7 6 5 4 – The FPDSCR holds the default values for the floating-point status control data. AHP: FPSCR.AHP Default Value Default value for FPSCR.AHP. DN: FPSCR.DN Default Value Default value for FPSCR.DN. FZ: FPSCR.
12.13 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned.
Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned.
Exception An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception.
Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Big-endian (BE)” , “Byte-invariant” , “Endianness” . Little-endian memory Memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address. See also “Big-endian memory” .
Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Undefined Indicates an instruction that generates an Undefined instruction exception. Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.
13. Debug and Test Features 13.1 Description The SAM4 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 13.
13.3 Debug and Test Block Diagram Figure 13-1.
13.4 Application Examples 13.4.1 Debug Environment Figure 13-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 13-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM4 SAM4-based Application Board 13.4.
Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM4 Chip 2 Chip 1 SAM4-based Application Board In Test 13.5 Debug and Test Pin Description Table 13-1.
13.6 Functional Description 13.6.1 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4E series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet. 13.6.
Figure 13-4. Debug Architecture DWT 4 watchpoints FPB SWJ-DP PC sampler 6 breakpoints data address sampler SWD/JTAG ITM data sampler software trace 32 channels interrupt trace SWO trace TPIU time stamping CPU statistics 13.6.5 Serial Wire JTAG Debug Port (SWJ-DP) Pins The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG connector defined by ARM.
13.6.5.1 SW-DP and JTAG-DP Selection Mechanism Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by default after reset. Switch from JTAG-DP to SW-DP. The sequence is: ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 ̶ Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first) ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 Switch from SWD to JTAG.
Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. 13.6.8.1 How to Configure the ITM The following example describes how to output trace data in asynchronous trace mode. Configure the TPIU for asynchronous trace mode (refer to Section 13.6.8.3 “5.4.3.
functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file to set up the test is provided on the Atmel website at http://www.atmel.com. 13.6.9.
13.6.10 ID Code Register Access: Read-only 31 30 29 28 27 21 20 19 PART NUMBER VERSION 23 22 15 14 13 PART NUMBER 7 6 5 12 11 4 3 MANUFACTURER IDENTITY 26 25 PART NUMBER 24 18 16 17 10 9 MANUFACTURER IDENTITY 2 1 VERSION[31:28]: Product Version Number Set to 0x0. PART NUMBER[27:12]: Product Part Number Chip Name SAM4E Chip ID 0xA3CC_0CE0 MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1.
14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.
14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST manager and a reset state manager. It runs at slow clock and generates the following reset signals: proc_nreset: processor reset line. It also resets the Watchdog Timer. periph_nreset: affects the whole set of embedded peripherals nrst_out: drives the NRST pin These reset signals are asserted by the Reset Controller, either on external events or on software action.
14.4.2.2 NRST External Reset Control The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST manager for a time programmed by field ERSTL in the RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) slow clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
14.4.4.2 Backup Reset A backup reset occurs when the chip exits from Backup mode. While exiting Backup mode, the vddcore_nreset signal is asserted by the Supply Controller. Field RSTTYP in the RSTC_SR is updated to report a backup reset. 14.4.4.3 User Reset The user reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the RSTC_MR. The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 slow clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a watchdog reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in the WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-6. Watchdog Reset SLCK MCK Any Freq.
14.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
14.5 Reset Controller (RSTC) User Interface Table 14-1.
14.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0x400E1800 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. EXTRST: External Reset 0: No effect.
14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0x400E1804 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0x400E1808 Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
15. Real-time Timer (RTT) 15.1 Description The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16bit prescaler driven from the 32-kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. The RTT can also be configured to be driven by the 1Hz RTC signal, thus taking advantage of a calibrated 1Hz clock.
Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a 1Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. Bit RTTINC in the “Real-time Timer Status Register” (RTT_SR) is set each time there is a prescaler roll-over (see Figure 15-2) The real-time 32-bit counter can also be supplied by the 1Hz RTC clock.
Figure 15-2. RTT Counting SLCK RTPRES - 1 Prescaler 0 CRTV 0 ...
15.5 Real-time Timer (RTT) User Interface Table 15-1.
15.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0x400E1830 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 RTC1HZ 23 – 22 – 21 – 20 RTTDIS 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SLCK periods.
15.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0x400E1834 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV ALMV: Alarm Value When the CRTV value in RTT_VR equals the ALMV field, the ALMS flag is set in RTT_SR. As soon as the ALMS flag rises, the CRTV value equals ALMV+1 (refer to Figure 15-2).
15.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0x400E1838 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
15.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0x400E183C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR.
16. Real-time Clock (RTC) 16.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus.
16.3 Block Diagram Figure 16-1. RTC Block Diagram Slow Clock: SLCK 32768 Divider Time Wave Generator Date RTCOUT0 RTCOUT1 Clock Calibration APB 16.4 User Interface Entry Control Alarm Interrupt Control RTC Interrupt Product Dependencies 16.4.1 Power Management The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior. 16.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller.
Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 16.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds.
Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the TDERR flag. The clearing of the source of such error can be done either by reprogramming a correct value on RTC_CALR and/or RTC_TIMR. The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e., every 10 seconds for SECONDS[3:0] field in RTC_TIMR).
Figure 16-2.
16.5.7 RTC Accurate Clock Calibration The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at room temperature (20–25°C).
The first selection choice sticks the associated output at 0 (This is the reset value and it can be used at any time to disable the waveform generation). Selection choices 1 to 4 respectively select 1 Hz, 32 Hz, 64 Hz and 512 Hz. 32 Hz or 64 Hz can drive, for example, a TN LCD backplane signal while 1 Hz can be used to drive a blinking character like “:” for basic time display (hour, minute) on TN LCDs. Selection choice 5 provides a toggling signal when the RTC alarm is reached.
16.6 Real-time Clock (RTC) User Interface Table 16-1.
16.6.1 RTC Control Register Name: RTC_CR Address: 0x400E1860 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). UPDTIM: Update Request Time Register 0: No effect.
CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 339
16.6.2 RTC Mode Register Name: RTC_MR Address: 0x400E1864 Access: Read/Write 31 30 – – 23 22 – 29 28 27 TPERIOD 21 20 19 OUT1 15 14 26 – 18 – 13 12 HIGHPPM 11 25 24 THIGH 17 16 OUT0 10 9 8 CORRECTION 7 6 5 4 3 2 1 0 – – – NEGPPM – – PERSIAN HRMOD This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected.
3906 CORRECTION = ----------------------- – 1 20 × ppm The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
Value Name Description 5 H_122US 122 µs 6 H_30US 30.5 µs 7 H_15US 15.
16.6.3 RTC Time Register Name: RTC_TIMR Address: 0x400E1868 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 MIN 6 5 – 11 4 3 SEC SEC: Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. MIN: Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units.
16.6.4 RTC Calendar Register Name: RTC_CALR Address: 0x400E186C Access: Read/Write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT CENT: Current Century The range that can be set is 19–20 (gregorian) or 13–14 (persian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. YEAR: Current Year The range that can be set is 00–99 (BCD).
16.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0x400E1870 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
16.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0x400E1874 Access: Read/Write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
16.6.7 RTC Status Register Name: RTC_SR Address: 0x400E1878 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERR CALEV TIMEV SEC ALARM ACKUPD ACKUPD: Acknowledge for Update Value Name Description 0 FREERUN Time and calendar registers cannot be updated. 1 UPDATE Time and calendar registers can be updated.
TDERR: Time and/or Date Free Running Error Value 348 Name Description 0 CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 1 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid.
16.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0x400E187C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). ALRCLR: Alarm Clear 0: No effect.
16.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0x400E1880 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERREN CALEN TIMEN SECEN ALREN ACKEN ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. ALREN: Alarm Interrupt Enable 0: No effect.
16.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0x400E1884 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. ALRDIS: Alarm Interrupt Disable 0: No effect.
16.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0x400E1888 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled.
16.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0x400E188C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed.
17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 17.
17.4 Functional Description The Watchdog Timer is used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode register (WDT_MR). The Watchdog Timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz).
Figure 17-2. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF if WDRSTEN is 0 Normal behavior WDV Forbidden Window WDD Permitted Window 0 WDT_CR.
17.5 Watchdog Timer (WDT) User Interface Table 17-1.
17.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0x400E1850 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the watchdog if KEY is written to 0xA5. KEY: Password. Value 0xA5 358 Name Description PASSWD Writing any other value in this field aborts the write operation.
17.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0x400E1854 Access: Read/Write Once 31 – 30 – 29 WDIDLEHLT 28 WDDBGHLT 27 23 22 21 20 19 11 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV Note: The first write access prevents any further modification of the value of this register. Read accesses remain possible.
1: The watchdog stops when the system is in idle state. WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.
17.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0x400E1858 Access Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF WDUNF: Watchdog Underflow 0: No watchdog underflow occurred since the last read of WDT_SR. 1: At least one watchdog underflow occurred since the last read of WDT_SR.
18. Reinforced Safety Watchdog Timer (RSWDT) 18.1 Description When two watchdog timers are implemented in a device, the second one, the Reinforced Safety Watchdog Timer (RSWDT), works in parallel with the Watchdog Timer (WDT) to reinforce safe watchdog operations. The Reinforced Safety Watchdog Timer (RSWDT) can be used to reinforce the safety level provided by the Watchdog Timer (WDT) in order to prevent system lock-up if the software becomes trapped in a deadlock.
18.3 Block Diagram Figure 18-1. Reinforced Safety Watchdog Timer Block Diagram main RC frequency main RC clock write RSWDT_MR RSWDT_MR WDV RSWDT_CR divider WDRSTT reload 1 0 12-bit Down Counter RSWDT_MR WDD Automatic selection [CKGR_MOR.MOSCRCEN = 0 and (WDT_MR.WDDIS or SUPC_MR.
18.4 Functional Description The Reinforced Safety Watchdog Timer (RSWDT) can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. The RSWDT is initialized with default values on processor reset, or power-on sequence and is disabled (its default mode) under such conditions. The RSWDT works in a distinct and fully independent mode from the Watchdog Timer (WDT).
Writing the RSWDT_MR reloads and restarts the down counter. The RSWDT is disabled after any power-on sequence. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the WDIDLEHLT and WDDBGHLT bits in the RSWDT_MR. Figure 18-2. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF if WDRSTEN is 0 Normal behavior WDV Forbidden Window WDD Permitted Window 0 RSWDT_CR.
18.5 Reinforced Safety Watchdog Timer (RSWDT) User Interface Table 18-1.
18.5.1 Reinforced Safety Watchdog Timer Control Register Name: RSWDT_CR Address: 0x400E1900 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the watchdog. KEY: Password Value Name Description 0xC4 PASSWD Writing any other value in this field aborts the write operation.
18.5.2 Reinforced Safety Watchdog Timer Mode Register Name: RSWDT_MR Address: 0x400E1904 Access: Read-write Once 31 30 23 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 11 22 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV Note: The first write access prevents any further modification of the value of this register, read accesses remain possible.
WDIDLEHLT: Watchdog Idle Halt 0: The watchdog runs when the system is in idle mode. 1: The watchdog stops when the system is in idle state. WDDIS: Watchdog Disable 0: Enables the watchdog timer. 1: Disables the watchdog timer.
18.5.3 Reinforced Safety Watchdog Timer Status Register Name: RSWDT_SR Address: 0x400E1908 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF WDUNF: Watchdog Underflow 0: No watchdog underflow occurred since the last read of RSWDT_SR. 1: At least one watchdog underflow occurred since the last read of RSWDT_SR.
19. Supply Controller (SUPC) 19.1 Description The Supply Controller (SUPC) controls the supply voltages of the system and manages the backup low-power mode. In this mode, current consumption is reduced to a few microamps for backup power retention. Exit from this mode is possible on multiple wake-up sources. The SUPC also generates the slow clock by selecting either the low-power RC oscillator or the low-power crystal oscillator. 19.
19.3 Block Diagram Figure 19-1.
19.4 Supply Controller Functional Description 19.4.1 Supply Controller Overview The device is divided into two power supply areas: The backup VDDIO power supply that includes the Supply Controller, a part of the Reset Controller, the slow clock switch, the general-purpose backup registers, the supply monitor and the clock which includes the Real-time Timer and the Real-time Clock.
19.4.2 Slow Clock Generator The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, depending on what the user selects. This can be configured by programming the SMSMPL field in SUPC_SMMR. Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by factors of 2, 16 and 128, respectively, if the user does not need a continuous monitoring of the VDDIO power supply.
signal to the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle. Figure 19-3. Raising the VDDIO Power Supply TON Voltage 7 x Slow Clock Cycles (5 for startup slow RC + 2 for synchro.) Regulator 3 x Slow Clock 2 x Slow Clock Cycles Cycles 6.
19.4.6.2 Brownout Detector Reset The brownout detector provides the bodcore_in signal to the SUPC which indicates that the voltage regulation is operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is enabled, the Supply Controller asserts vddcore_nreset if BODRSTEN is written to 1 in SUPC_MR.
If the FWUP pin is asserted for a time longer than the debouncing period, a wake-up of the core power supply is started and the FWUP bit in SUPC_SR is set and remains high until the register is read. 19.4.7.2 Wake-up Inputs The wake-up inputs, WKUPx, can be programmed to perform a wake-up of the core power supply. Each input can be enabled by writing to 1 the corresponding bit, WKUPENx, in the Wake-up Inputs register (SUPC_WUIR).
Figure 19-5. Low-power Debouncer (Push-to-Make Switch, Pull-up Resistors) MCU RTCOUTx Pull-up Resistor WKUP0 Pull-up Resistor GND WKUP1 GND GND Figure 19-6. Low-power Debouncer (Push-to-Break Switch, Pull-down Resistors) MCU RTCOUTx WKUP0 WKUP1 Pull-down Resistors GND GND GND The debouncing period duration is configurable. The period is made for all debouncers (i.e., the duration cannot be adjusted separately for each debouncer).
tamper detection circuitry. If RTCOUTx is not used, the RTC must be configured to create an internal sampling point for the debouncer logic. The period of time between two samples can be configured by programming the TPERIOD field in RTC_MR. Figure 19-7 illustrates the use of WKUPx without the RTCOUTx pin. Figure 19-7. Using WKUP Pins Without RTCOUTx Pins VDDIO MCU Pull-up Resistor WKUP0 Pull-up Resistor GND WKUP1 GND GND 19.4.7.
”Supply Controller Mode Register” ”Supply Controller Wake-up Mode Register” ”Supply Controller Wake-up Inputs Register” 19.4.
19.5 Supply Controller (SUPC) User Interface The user interface of the Supply Controller is part of the System Controller user interface. 19.5.1 System Controller (SYSC) User Interface Table 19-1.
19.5.3 Supply Controller Control Register Name: SUPC_CR Address: 0x400E1810 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 XTALSEL 2 VROFF 1 – 0 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR). VROFF: Voltage Regulator Off 0 (NO_EFFECT): No effect.
19.5.4 Supply Controller Supply Monitor Mode Register Name: SUPC_SMMR Address: 0x400E1814 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SMIEN 12 SMRSTEN 11 – 10 9 SMSMPL 8 7 – 6 – 5 – 4 – 3 2 1 0 SMTH This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).
19.5.5 Supply Controller Mode Register Name: SUPC_MR Address: 0x400E1818 Access: Read/Write 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 OSCBYPASS 19 – 18 – 17 – 16 – 15 14 ONREG 13 BODDIS 12 BODRSTEN 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).
19.5.6 Supply Controller Wake-up Mode Register Name: SUPC_WUMR Address: 0x400E181C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LPDBC 16 15 – 14 13 WKUPDBC 12 11 – 10 9 FWUPDBC 8 7 LPDBCCLR 6 LPDBCEN1 5 LPDBCEN0 4 – 3 RTCEN 2 RTTEN 1 SMEN 0 FWUPEN This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).
LPDBCCLR: Low-power Debouncer Clear 0 (NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of GPBR registers. 1 (ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers.
19.5.
19.5.
SMOS: Supply Monitor Output Status 0 (HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement. 1 (LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement. OSCSEL: 32-kHz Oscillator Selection Status 0 (RC): The slow clock, SLCK is generated by the embedded 32 kHz RC oscillator. 1 (CRYST): The slow clock, SLCK is generated by the 32 kHz crystal oscillator. FWUPIS: FWUP Input Status 0 (LOW): FWUP input is tied low.
19.5.9 System Controller Write Protection Mode Register Name: SYSC_WPMR Access: Read/Write Reset: See Table 19-1 ”System Controller Registers” 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
20. General Purpose Backup Registers (GPBR) 20.1 Description The System Controller embeds 20 General Purpose Backup registers. It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 9 (first half) if a Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other General Purpose Backup registers (second half) remains unchanged. The Supply Controller module must be programmed accordingly.
20.3 General Purpose Backup Registers (GPBR) User Interface Table 20-1. Offset 0x0 ... 0x64 Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 19 SYS_GPBR19 Access Reset Read/Write 0x00000000 ... ...
20.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0x400E1890 Access: Read/Write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 GPBR_VALUE 23 22 21 20 19 GPBR_VALUE 15 14 13 12 11 GPBR_VALUE 7 6 5 4 3 GPBR_VALUE These registers are reset at first power-up and on each loss of VDDBU.
21. Enhanced Embedded Flash Controller (EEFC) 21.1 Description The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
Two 128-bit or 64-bit read buffers used for code read optimization One 128-bit or 64-bit read buffer used for data read optimization One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final address. Several lock bits used to protect write/erase operation on several pages (lock region).
21.4.2 Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb-2 mode by means of the 128- or 64-bit-wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it.
Figure 21-3.
21.4.2.4 Data Read Optimization The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order to store the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure 21-5). The data read optimization is enabled by default.
Table 21-2. Set of Commands Command Value Mnemonic Start read unique identifier 0x0E STUI Stop read unique identifier 0x0F SPUI Get CALIB bit 0x10 GCALB Erase sector 0x11 ES Write user signature 0x12 WUS Erase user signature 0x13 EUS Start read user signature 0x14 STUS Stop read user signature 0x15 SPUS In order to perform one of these commands, the Flash Command register (EEFC_FCR) must be written with the correct command using the FCMD field.
Figure 21-6. Command State Chart Read Status: MC_FSR No Check if FRDY flag Set Yes Write FCMD and PAGENB in Flash Command Register Read Status: MC_FSR No Check if FRDY flag Set Yes Check if FLOCKE flag Set Yes Locking region violation No Check if FCMDE flag Set Yes Bad keyword violation No Command Successfull 21.4.3.1 Get Flash Descriptor Command This command provides the system with information on the Flash organization. The system can take full advantage of this information.
Table 21-3. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash interface description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes. FL_PLANE[0] 4 Number of bytes in the plane. FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is used to prevent write or erase operations in the lock region. FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region. 21.
Only one page can be programmed at a time. It is possible to program all the bits of a page (full page programming) or only some of the bits of the page (partial page programming). Depending on the number of bits to be programmed within the page, the EEFC adapts the write operations required to program the Flash. When the Programming Page command is given, the EEFC starts the programming sequence and all the bits written at 0 in the latch buffer are cleared in the Flash memory array. During programming, i.
Figure 21-7.
Figure 21-8.
Figure 21-9.
When programming is completed, the FRDY bit in EEFC_FSR rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the interrupt controller is activated. Three errors can be detected in EEFC_FSR after a programming sequence: Command Error: a bad keyword has been written in EEFC_FCR. Lock Error: at least one page to be erased belongs to a locked region. The erase command has been refused, no page has been erased.
21.4.3.5 GPNVM Bit GPNVM bits do not interfere with the embedded Flash memory plane. Refer to specific product details for information on GPNVM bit action. The Set GPNVM bit sequence is: Start the Set GPNVM bit command (SGPB) by writing EEFC_FCR with the SGPB command and the number of the GPNVM bits to be set. When the GPNVM bit is set, the bit FRDY in EEFC_FSR rises. If an interrupt was enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the interrupt controller is activated.
Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. The 4/8/12 MHz fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB bit command. The table below shows the bit implementation for each frequency: Table 21-5.
One error can be detected in EEFC_FSR after this sequence: Command Error: a bad keyword has been written in EEFC_FCR. To write the user signature, the sequence is: Write the full page, at any page address, within the internal memory area address space. Send the Write user signature command (WUS) by writing EEFC_FCR with the WUS command. When programming is completed, the FRDY bit in EEFC_FSR rises.
21.5 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0A00. Table 21-6.
21.5.1 EEFC Flash Mode Register Name: EEFC_FMR Address: 0x400E0A00 Access: Read/Write Offset: 0x00 31 30 29 28 27 26 25 24 – – – – – CLOE – FAM 23 22 21 20 19 18 17 16 – – – – – – – SCOD 15 14 13 12 11 10 9 8 – – – – 7 6 5 4 3 2 1 0 – – – – – – – FRDY FWS FRDY: Ready Interrupt Enable 0: Flash ready does not generate an interrupt. 1: Flash ready (to accept a new command) generates an interrupt.
21.5.
FARG: Flash Command Argument GETD, GLB, GGPB, STUI, SPUI, GCALB, WUS, EUS, STUS, SPUS, EA Commands requiring no argument, including Erase all command FARG is meaningless, must be written with 0 ES Erase sector command FARG must be written with any page number within the sector to be erased FARG[1:0] defines the number of pages to be erased The start page must be written in FARG[15:2]. FARG[1:0] = 0: Four pages to be erased.
21.5.3 EEFC Flash Status Register Name: EEFC_FSR Address: 0x400E0A08 Access: Read-only Offset: 0x08 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – FLERR FLOCKE FCMDE FRDY FRDY: Flash Ready Status 0: The EEFC is busy. 1: The EEFC is ready to start a new command. When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR.
21.5.4 EEFC Flash Result Register Name: EEFC_FRR Address: 0x400E0A0C Access: Read-only Offset: 0x0C 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FVALUE 23 22 21 20 FVALUE 15 14 13 12 FVALUE 7 6 5 4 FVALUE FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read.
22. Fast Flash Programming Interface (FFPI) 22.1 Description The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
22.3 Parallel Fast Flash Programming 22.3.1 Device Configuration In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left unconnected. Figure 22-1. SAM4ExE Parallel Programming Interface VDDIO VDDIO VDDIO TST PGMEN0 PGMEN1 VDDCORE NCMD RDY PGMNCMD PGMRDY NOE PGMNOE NVALID Table 22-1.
Table 22-1.
Table 22-3. Command Bit Coding (Continued) DATA[15:0] Symbol Command Executed 0x0035 GSE Get Security Bit 0x001F WRAM Write Memory 0x001E GVE Get Version 22.3.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: Apply the supplies as described in Table 22-1. Apply XIN clock within TPOR_RESET if an external clock is available. Wait for TPOR_RESET Start a read or write handshaking.
Figure 22-3. Parallel Programming Timing, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[15:0] 1 MODE[3:0] Table 22-4.
Figure 22-5. Parallel Programming Timing, Read Sequence NCMD 12 2 3 RDY 13 NOE 9 5 NVALID 11 7 6 4 Adress IN DATA[15:0] Z 8 Data OUT 10 X IN 1 MODE[3:0] Table 22-5.
22.3.5.1 Flash Read Command This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 22-6.
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 22.3.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The generalpurpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. Table 22-11. Set/Clear GP NVM Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE SGPB or CGPB 2 Write handshaking DATA GP NVM bit pattern value General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB).
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 22-14. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE WRAM 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking DATA *Memory Address++ 5 Write handshaking DATA *Memory Address++ ... ... ... ...
23. Cortex M Cache Controller (CMCC) 23.1 Description The Cortex M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a controller, a tag directory, data memory, metadata memory and a configuration interface. 23.
23.3 Block Diagram Figure 23-1. Block Diagram Cortex M Memory Interface Bus Cortex M Interface Cache Controller APB Interface METADATA RAM RAM Interface Registers Interface DATA RAM TAG RAM Memory Interface System Memory Bus 23.4 Functional Description 23.4.1 Cache Operation On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated with its configuration registers.
3. Perform an invalidate by line writing the bit set {index, way} in the CMCC_MAINT1 register. 4. Enable the cache controller, writing 1 to the CEN field of the CMCC_CTRL register. 23.4.2.2 Cache Invalidate All Operation To invalidate all cache entries: Write 1 to the INVALL field of the CMCC_MAINT0 register. 23.4.3 Cache Performance Monitoring The Cortex M cache controller includes a programmable 32-bit monitor counter.
23.5 Cortex M Cache Controller (CMCC) User Interface Table 23-1.
23.5.1 Cache Controller Type Register Name: CMCC_TYPE Address: 0x400C4000 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 12 CLSIZE 11 10 9 CSIZE 8 7 LCKDOWN 6 5 4 RRP 3 LRUP 2 RANDP 1 GCLK 0 AP WAYNUM AP: Access Port Access Allowed 0: Access Port Access is disabled. 1: Access Port Access is enabled. GCLK: Dynamic Clock Gating Supported 0: Cache controller does not support clock gating.
LCKDOWN: Lock Down Supported 0: Lock Down is not supported. 1: Lock Down is supported.
23.5.2 Cache Controller Configuration Register Name: CMCC_CFG Address: 0x400C4004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 GCLKDIS GCLKDIS: Disable Clock Gating 0: Clock gating is activated. 1: Clock gating is disabled.
23.5.3 Cache Controller Control Register Name: CMCC_CTRL Address: 0x400C4008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CEN CEN: Cache Controller Enable 0: When set to 0, this field disables the cache controller. 1: When set to 1, this field enables the cache controller.
23.5.4 Cache Controller Status Register Name: CMCC_SR Address: 0x400C400C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CSTS CSTS: Cache Controller Status 0: When read as 0, this field indicates that the cache controller is disabled. 1: When read as 1, this field indicates that the cache controller is enabled.
23.5.5 Cache Controller Maintenance Register 0 Name: CMCC_MAINT0 Address: 0x400C4020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INVALL INVALL: Cache Controller Invalidate All 0: No effect. 1: When set to 1, this field invalidates all cache entries.
23.5.6 Cache Controller Maintenance Register 1 Name: CMCC_MAINT1 Address: 0x400C4024 Access: Write-only 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INDEX 7 6 5 4 3 – 2 – 1 – 0 – WAY INDEX INDEX: Invalidate Index This field indicates the cache line that is being invalidated.
23.5.
23.5.8 Cache Controller Monitor Enable Register Name: CMCC_MEN Address: 0x400C402C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MENABLE MENABLE: Cache Controller Monitor Enable 0: When set to 0, the monitor counter is disabled. 1: When set to 1, the monitor counter is activated.
23.5.9 Cache Controller Monitor Control Register Name: CMCC_MCTRL Address: 0x400C4030 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST SWRST: Monitor 0: No effect. 1: When set to 1, this field resets the event counter register.
23.5.
24. SAM-BA Boot Program for SAM4E Microcontrollers 24.1 Description The SAM-BA® Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 24.
24.4 Flow Diagram The Boot Program implements the algorithm in Figure 24-1. Figure 24-1. Boot Program Algorithm Flow Diagram No Device Setup No USB Enumeration Successful ? Character # received from UART0? Yes Yes Run SAM-BA Monitor Run SAM-BA Monitor The SAM-BA Boot program seeks to detect a source clock either from the embedded main oscillator with external crystal (main oscillator enabled) or from a supported frequency signal applied to the XIN pin (Main oscillator in bypass mode).
24.6 SAM-BA Monitor The SAM-BA boot principle: Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown in Table 24-2. Table 24-2.
24.6.1 UART0 Serial Port Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work.
For More details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the USB Implementers Forum: http://www.usb.org/developers/vendor/VID_Only_Form_withCCAuth_102407b.pdf "Unauthorized use of assigned or unassigned USB Vendor ID Numbers and associated Product ID Numbers is strictly prohibited." Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys.
24.6.4 In Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash.
25. Bus Matrix (MATRIX) 25.1 Description The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 7 AHB masters to up to 6 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
Table 25-1. List of Bus Matrix Slaves (Continued) Slave 3 Peripheral Bridge 0 Slave 4 Peripheral Bridge 1 Slave 5 External Bus Interface (EBI) 25.2.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M4 S Bus to the Internal SRAM. Thus, these paths are forbidden or simply not wired, and shown as “–” in Table 25-2. Table 25-2.
25.3 Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR), that performs remap action for every master independently.
25.6 Last Access Master After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between.
25.8.1.1 Undefined Length Burst Arbitration In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the following Undefined Length Burst Type (ULBT) possibilities: 1. Unlimited: no predetermined end of burst is generated. This value enables 1-Kbyte burst lengths. 2.
After reset, all the masters belong to the lowest priority pool (MxPR = 0) and are therefore granted bus access in a true round-robin order. The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight and deterministic maximum access latency from AHB bus requests.
25.11 Write Protect Registers To prevent any single software error that may corrupt the Bus Matrix behavior, the entire Bus Matrix address space can be write-protected by setting the WPEN bit in the Bus Matrix Write Protect Mode Register (MATRIX_WPMR). If WPEN is at one and a write access in the Bus Matrix address space is detected, then the WPVS flag in the Bus Matrix Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
25.12 Bus Matrix (MATRIX) User Interface Table 25-3.
Table 25-3. Register Mapping (Continued) Offset Register 0x0128 - 0x01E0 Reserved – Access Reset – – 0x01E4 Write Protect Mode Register MATRIX_WPMR Read-write 0x00000000 0x01E8 Write Protect Status Register MATRIX_WPSR Read-only 0x00000000 Notes: 456 Name 1. Values in the Bus Matrix Priority Registers are product dependent.
25.12.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFGx [x=0..6] Address: 0x400E0200 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
25.12.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFGx [x=0..5] Address: 0x400E0240 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – 15 14 13 12 11 10 9 8 – – – – – – – SLOT_CYCLE 7 6 5 4 3 2 1 0 FIXED_DEFMSTR DEFMSTR_TYPE SLOT_CYCLE This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
25.12.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRASx [x=0..
25.12.4 Bus Matrix Master Remap Control Register Name: MATRIX_MRCR Address: 0x400E0300 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
25.12.5 System I/O Configuration Register Name: CCFG_SYSIO Address: 0x400E0314 Access: Read-write Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SYSIO12 SYSIO11 SYSIO10 – – 7 6 5 4 3 2 1 0 SYSIO7 SYSIO6 SYSIO5 SYSIO4 – – – – SYSIO4: PB4 or TDI Assignment 0 = TDI function selected. 1 = PB4 function selected.
25.12.
25.12.7 Write Protect Mode Register Name: MATRIX_WPMR Address: 0x400E03E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, please refer to Section 25.11 “Write Protect Registers”.
25.12.8 Write Protect Status Register Name: MATRIX_WPSR Address: 0x400E03E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, please refer to Section 25.11 “Write Protect Registers”. WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR.
26. DMA Controller (DMAC) 26.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer.
26.3 DMA Controller Peripheral Connections The DMA Controller handles the transfer between peripherals and memory and receives triggers from the peripherals listed in table that follows. Table 26-1.
26.4 Block Diagram Figure 26-1.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel.
Figure 26-3. DMAC Transfer Hierarchy for Memory DMAC Transfer Buffer AMBA Burst Transfer Buffer AMBA Burst Transfer DMA Transfer Level Buffer AMBA Burst Transfer AMBA Single Transfer Buffer Transfer Level AMBA Transfer Level Buffer: A buffer of DMAC data. The amount of data (length) is determined by the flow controller. For transfers between the DMAC and memory, a buffer is broken directly into a sequence of AMBA bursts and AMBA single transfers.
26.5.2 Memory Peripherals Figure 26-3 on page 470 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled.
26.5.4 DMAC Transfer Types A DMAC transfer may consist of single or multi-buffer transfers.
Figure 26-4. Multi Buffer Transfer Using Linked List System Memory LLI(1) LLI(0) DSCRx(0) DSCRx(1)= DSCRx(0) + 0x10 DSCRx(2)= DSCRx(1) + 0x10 CTRLBx= DSCRx(0) + 0xC CTRLBx= DSCRx(1) + 0xC CTRLAx= DSCRx(0) + 0x8 CTRLBx= DSCRx(1) + 0x8 DADDRx= DSCRx(0) + 0x4 DADDRx= DSCRx(1) + 0x4 SADDRx= DSCRx(1) + 0x0 SADDRx= DSCRx(0) + 0x0 DSCRx(2) (points to 0 if LLI(1) is the last transfer descriptor DSCRx(1) 26.5.4.2 Programming DMAC for Multiple Buffer Transfers Table 26-3.
26.5.4.3 Ending Multi-buffer Transfers All multi-buffer transfers must end as shown in Row 1 of Table 26-3. At the end of every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last buffer and the DMAC transfer is terminated. For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so that LLI.DMAC_DSCRx is set to 0. 26.5.
5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 6. Once the transfer completes, the hardware sets the interrupts and disables the channel.
Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the DMAC_DSCRx(0). 13. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripheral).
Figure 26-6. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous Address of Source Layer Address of Destination Layer Buffer 2 DADDR(3) Buffer 2 Buffer 2 SADDR(3) DADDR(2) Buffer 2 Buffer 1 SADDR(2) DADDR(1) Buffer 1 SADDR(1) Buffer 0 DADDR(0) Buffer 0 SADDR(0) Source Buffers Destination Buffers The DMAC transfer flow is shown in Figure 26-7 on page 478.
Figure 26-7.
Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. 2. Set up the transfer characteristics, such as: ̶ 1. ̶ 3. i. Transfer width for the source in the SRC_WIDTH field. ii. Transfer width for the destination in the DST_WIDTH field. ̶ v. Incrementing/decrementing or fixed address for source in SRC_INCR field. ̶ vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 16.
Figure 26-9. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address Channel enabled by software LLI Fetch Hardware reprograms SADDRx, CTRLAx,CTRLBx, DSCRx DMAC buffer transfer Writeback of control information of LLI Buffer Transfer Completed Interrupt generated here Is DMAC in Row 1 ? DMAC Chained Buffer Transfer Completed Interrupt generated here no yes Channel disabled by hardware 26.5.
1. If the software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. 2. The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the channel n FIFO is empty, where n is the channel number. 3. The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO is empty, where n is the channel number.
Multiple Transfers involving the same peripheral must not be programmed and enabled on different channels, unless this peripheral integrates several hardware handshaking interfaces. When a Peripheral has been defined as the flow controller, the targeted DMAC Channel must be enabled before the Peripheral. If you do not ensure this and the First DMAC request is also the last transfer, the DMAC Channel might miss a Last Transfer Flag.
26.7 Write Protection Registers To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be writeprotected by setting the WPEN bit in the “DMAC Write Protect Mode Register” (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted.
26.8 DMA Controller (DMAC) User Interface Table 26-4.
26.8.1 DMAC Global Configuration Register Name: DMAC_GCFG Address: 0x400C0000 Access: Read-write Reset: 0x00000010 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ARB_CFG 3 – 2 – 1 – 0 – Note: Bit fields 0, 1, 2, and 3 have a default value of 0. This should not be changed. This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
26.8.2 DMAC Enable Register Name: DMAC_EN Address: 0x400C0004 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” . ENABLE: General Enable of DMA 0: DMA Controller is disabled. 1: DMA Controller is enabled.
26.8.3 DMAC Software Single Request Register Name: DMAC_SREQ Address: 0x400C0008 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 DSREQ3 6 SSREQ3 5 DSREQ2 4 SSREQ2 3 DSREQ1 2 SSREQ1 1 DSREQ0 0 SSREQ0 DSREQx: Destination Request Request a destination single transfer on channel i. SSREQx: Source Request Request a source single transfer on channel i.
26.8.4 DMAC Software Chunk Transfer Request Register Name: DMAC_CREQ Address: 0x400C000C Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i.
26.8.
26.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register Name: DMAC_EBCIER Address: 0x400C0018 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 – 14 – 13 – 12 – 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 – 6 – 5 – 4 – 3 BTC3 2 BTC2 1 BTC1 0 BTC0 BTCx: Buffer Transfer Completed [3:0] Buffer Transfer Completed Interrupt Enable Register.
26.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register Name: DMAC_EBCIDR Address: 0x400C001C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 – 14 – 13 – 12 – 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 – 6 – 5 – 4 – 3 BTC3 2 BTC2 1 BTC1 0 BTC0 BTCx: Buffer Transfer Completed [3:0] Buffer transfer completed Disable Interrupt Register.
26.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register Name: DMAC_EBCIMR Address: 0x400C0020 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 – 14 – 13 – 12 – 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 – 6 – 5 – 4 – 3 BTC3 2 BTC2 1 BTC1 0 BTC0 BTCx: Buffer Transfer Completed [3:0] 0: Buffer Transfer Completed Interrupt is disabled for channel i.
26.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register Name: DMAC_EBCISR Address: 0x400C0024 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 – 14 – 13 – 12 – 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 – 6 – 5 – 4 – 3 BTC3 2 BTC2 1 BTC1 0 BTC0 BTCx: Buffer Transfer Completed [3:0] When BTC[i] is set, Channel i buffer transfer has terminated.
26.8.10 DMAC Channel Handler Enable Register Name: DMAC_CHER Address: 0x400C0028 Access: Write-only 31 – 30 – 29 – 28 – 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 – 6 – 5 – 4 – 3 ENA3 2 ENA2 1 ENA1 0 ENA0 ENAx: Enable [3:0] When set, a bit of the ENA field enables the relevant channel.
26.8.11 DMAC Channel Handler Disable Register Name: DMAC_CHDR Address: 0x400C002C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RES3 10 RES2 9 RES1 8 RES0 7 – 6 – 5 – 4 – 3 DIS3 2 DIS2 1 DIS1 0 DIS0 DISx: Disable [3:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated.
26.8.12 DMAC Channel Handler Status Register Name: DMAC_CHSR Address: 0x400C0030 Access: Read-only Reset: 0x00FF0000 31 – 30 – 29 – 28 – 27 STAL3 26 STAL2 25 STAL1 24 STAL0 23 – 22 – 21 – 20 – 19 EMPT3 18 EMPT2 17 EMPT1 16 EMPT0 15 – 14 – 13 – 12 – 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 – 6 – 5 – 4 – 3 ENA3 2 ENA2 1 ENA1 0 ENA0 ENAx: Enable [3:0] A one in any position of this field indicates that the relevant channel is enabled.
26.8.13 DMAC Channel x [x = 0..3] Source Address Register Name: DMAC_SADDRx [x = 0..3] Address: 0x400C003C [0], 0x400C0064 [1], 0x400C008C [2], 0x400C00B4 [3] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADDR 23 22 21 20 SADDR 15 14 13 12 SADDR 7 6 5 4 SADDR This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
26.8.14 DMAC Channel x [x = 0..3] Destination Address Register Name: DMAC_DADDRx [x = 0..3] Address: 0x400C0040 [0], 0x400C0068 [1], 0x400C0090 [2], 0x400C00B8 [3] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DADDR 23 22 21 20 DADDR 15 14 13 12 DADDR 7 6 5 4 DADDR This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
26.8.15 DMAC Channel x [x = 0..3] Descriptor Address Register Name: DMAC_DSCRx [x = 0..3] Address: 0x400C0044 [0], 0x400C006C [1], 0x400C0094 [2], 0x400C00BC [3] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 DSCR 23 22 21 20 DSCR 15 14 13 12 DSCR 7 6 5 4 DSCR This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
26.8.16 DMAC Channel x [x = 0..3] Control A Register Name: DMAC_CTRLAx [x = 0..
26.8.17 DMAC Channel x [x = 0..3] Control B Register Name: DMAC_CTRLBx [x = 0..3] Address: 0x400C004C [0], 0x400C0074 [1], 0x400C009C [2], 0x400C00C4 [3] Access: Read-write Reset: 0x00000000 31 – 30 IEN 23 – 22 15 – 7 – 29 28 DST_INCR 27 – 26 – 25 24 SRC_INCR 21 20 DST_DSCR 19 – 18 – 17 – 16 SRC_DSCR 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – FC This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination Value Name Description 00 INCREMENTING The destination address is incremented 01 DECREMENTING The destination address is decremented 10 FIXED The destination address remains unchanged IEN: Interrupt Enable Not 0: When the buffer transfer is completed, the BTCx flag is set in the EBCISR status register. This bit is active low. 1: When the buffer transfer is completed, the BTCx flag is not set.
26.8.18 DMAC Channel x [x = 0..3] Configuration Register Name: DMAC_CFGx [x = 0..
LOCK_IF_L: Master Interface Arbiter Lock 0 (CHUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 (BUFFER): The Master Interface Arbiter is locked by the channel x for a buffer transfer. AHB_PROT: AHB Protection AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of protection.
26.8.19 DMAC Write Protect Mode Register Name: DMAC_WPMR Address: 0x400C01E4 Access: Read-write Reset: See Table 26-4 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII).
26.8.20 DMAC Write Protect Status Register Name: DMAC_WPSR Address: 0x400C01E8 Access: Read-only Reset: See Table 26-4 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register.
27. Peripheral DMA Controller (PDC) 27.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the target memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
27.3 Peripheral DMA Controller Connections The Peripheral DMA Controller is composed of two PDCs (PDC0 and PDC1) which handle the data transfer between peripherals and memory and receive triggers from the peripherals listed in tables that follow. 27.3.1 Peripheral DMA Controller 0 (PDC0) The Peripheral DMA Controller 0 handles transfer requests from the channel according to the following priorities (Channel 0 is high priority): Table 27-1.
27.3.2 Peripheral DMA Controller 1 (PDC1) The Peripheral DMA Controller 1 handles transfer requests from the channel according to the following priorities (Channel 0 is high priority): Table 27-2.
27.4 Block Diagram Figure 27-1.
27.5 Functional Description 27.5.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full- or half-duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
ENDTX flag is set when the PDC Transmit Counter register (PERIPH_TCR) reaches zero. TXBUFE flag is set when both PERIPH_TCR and the PDC Transmit Next Counter register (PERIPH_TNCR) reach zero. These status flags are described in the Peripheral Status register (PERIPH_PTSR). 27.5.
27.6 Peripheral DMA Controller (PDC) User Interface Table 27-3.
27.6.1 Receive Pointer Register Name: PERIPH_RPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
27.6.2 Receive Counter Register Name: PERIPH_RCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the receiver.
27.6.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
27.6.4 Transmit Counter Register Name: PERIPH_TCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the transmitter.
27.6.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR RXNPTR: Receive Next Pointer RXNPTR contains the next receive buffer address. When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
27.6.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR RXNCTR: Receive Next Counter RXNCTR contains the next receive buffer size. When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
27.6.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR TXNPTR: Transmit Next Pointer TXNPTR contains the next transmit buffer address. When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
27.6.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR TXNCTR: Transmit Counter Next TXNCTR contains the next transmit buffer size. When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
27.6.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set.
27.6.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN RXTEN: Receiver Transfer Enable 0: PDC receiver channel requests are disabled. 1: PDC receiver channel requests are enabled. TXTEN: Transmitter Transfer Enable 0: PDC transmitter channel requests are disabled.
28. Static Memory Controller (SMC) 28.1 Description The External Bus Interface is designed to ensure the successful data transfer between several external devices and the Cortex-M4 based device. The External Bus Interface of the CM4P2 consists of a Static Memory Controller (SMC). This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
28.3 I/O Lines Description Table 28-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWE Write Enable Signal Output Low A[23:0] Address Bus Output D[7:0] Data Bus NWAIT External Wait Signal NANDCS I/O Input Low NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low 28.4 Product Dependencies 28.4.
Figure 28-1. Memory Connections for Four External Devices NCS[0] - NCS[3] NRD SMC NWE A[23:0] D[7:0] NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable 24 8 28.6 A[23:0] D[7:0] Connection to External Devices 28.6.1 Data Bus Width The data bus width is 8 bits. Figure 28-2 shows how to connect a 512K x 8-bit memory on NCS0. Figure 28-2.
Figure 28-3. NAND Flash Signal Multiplexing on SMC Pins SMC NAND Flash Logic NCSx (activated if SMC_NFCSx=1) * NRD NANDOE NANDWE NANDOE NANDWE NWE * in CCFG_SMCNFCS Matrix register Note: When NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used i PIO Mode but only in peripheral mode (NWE function). If NWE function is not used for other external memories (SRAM, LCD), it must be configured in one of the following modes.
Figure 28-4. Standard and “CE don’t care” NAND Flash Application Examples D[7:0] D[7:0] AD[7:0] A[22:21] A[22:21] ALE CLE NCSx NCSx CE SMC NAND Flash “CE don’t care” NAND Flash NANDOE NANDOE NOE NANDWE 28.7 ALE CLE Not Connected SMC AD[7:0] NOE NANDWE NWE PIO CE PIO R/B PIO NWE R/B Application Example 28.7.1 Implementation Examples Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check for memory device availability.
28.7.1.1 8-bit NAND Flash Hardware Configuration D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K K9F2G08U0M I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
28.7.1.2 NOR Flash Hardware Configuration D[0..7] A[0..
Figure 28-5. Standard Read Cycle MCK A[23:0] NRD NCS D[7:0] NRD_SETUP NCS_RD_SETUP NRD_PULSE NCS_RD_PULSE NRD_HOLD NCS_RD_HOLD NRD_CYCLE 28.8.1.1 NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3.
28.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 28-6). Figure 28-6. No Setup, No Hold on NRD and NCS Read Signals MCK A[23:0] NRD NCS D[7:0] NRD_PULSE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE NRD_CYCLE 28.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1.
Figure 28-7. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[23:0] NRD NCS tPACC D[7:0] Data Sampling 28.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 28-8 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised.
28.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 28-9. The write cycle starts with the address setting on the memory address bus. 28.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3.
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 28.8.3.4 Null Delay Setup and Hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 28-10). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 28-10.
Figure 28-11. WRITE_MODE = 1. The write operation is controlled by NWE MCK A[23:0] NWE NCS D[7:0] 28.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 28-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 28-12. WRITE_MODE = 0.
Section 28.15.3 “SMC Cycle Register” Section 28.15.4 “SMC MODE Register” 28.8.6 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.
For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 540. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus.
Figure 28-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[23:0] NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[7:0] Read to Write Wait State Chip Select Wait State 28.10.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state.
Figure 28-14. Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[23:0] NWE NRD no hold no setup D[7:0] write cycle Early Read wait state read cycle Figure 28-15.
Figure 28-16. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[7:0] write cycle Early Read read cycle (WRITE_MODE = 1) wait state (READ_MODE = 0 or READ_MODE = 1) 28.10.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
28.10.3.2Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 554). 28.10.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document.
28.11 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: before starting a read access to a different external memory before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select.
Figure 28-18. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[23:0] NRD NCS tpacc D[7:0] TDF = 3 clock cycles NCS controlled read operation 28.11.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
Figure 28-19. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[7:0] read access on NCS0 (NRD controlled) Read to Write Wait State write access on NCS0 (NWE controlled) 28.11.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins.
Figure 28-20. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[23:0] read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[7:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 28-21.
Figure 28-22. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[23:0] read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[7:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 28.12 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
28.12.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 28-23.
Figure 28-24.
28.12.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 28-25 and Figure 28-26. After deassertion, the access is completed: the hold step of the access is performed.
Figure 28-26.
28.12.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
28.13 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
28.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 28-29 on page 555. The external device may not be fast enough to support such timings. Figure 28-30 illustrates the recommended procedure to properly switch from one mode to the other. Figure 28-29.
28.14 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
In page mode, the programming of the read timings is described in Table 28-6: Table 28-6. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
Figure 28-32.
28.15 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 28-7. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 28-7, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 28-7.
28.15.1 SMC Setup Register Name: SMC_SETUP[0..
28.15.2 SMC Pulse Register Name: SMC_PULSE[0..
28.15.3 SMC Cycle Register Name: SMC_CYCLE[0..3] Address: 0x40060008 [0], 0x40060018 [1], 0x40060028 [2], 0x40060038 [3] Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
28.15.4 SMC MODE Register Name: SMC_MODE[0..3] Address: 0x4006000C [0], 0x4006001C [1], 0x4006002C [2], 0x4006003C [3] Access: Read-write 31 30 – – 29 28 23 22 21 20 – – – TDF_MODE 15 14 13 12 11 – – – – – 7 6 5 4 3 2 1 0 – – – – WRITE_MODE READ_MODE PS EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 10 9 8 – – – TDF_CYCLES READ_MODE: 1: The read operation is controlled by the NRD signal.
TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. TDF_MODE: TDF Optimization 1: TDF optimization is enabled.
28.15.5 SMC OCMS Mode Register Name: SMC_OCMS Address: 0x40060080 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CS3SE 18 CS2SE 17 CS1SE 16 CS0SE 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 - 0 SMSE CSxSE: Chip Select (x = 0 to 3) Scrambling Enable 0: Disable Scrambling for CSx. 1: Enable Scrambling for CSx.
28.15.6 SMC OCMS Key1 Register Name: SMC_KEY1 Address: 0x40060084 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1 23 22 21 20 KEY1 15 14 13 12 KEY1 7 6 5 4 KEY1 KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY1 and KEY2 values.
28.15.7 SMC OCMS Key2 Register Name: SMC_KEY2 Address: 0x40060088 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2 23 22 21 20 KEY2 15 14 13 12 KEY2 7 6 5 4 KEY2 KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values.
28.15.8 SMC Write Protect Mode Register Name: SMC_WPMR Address: 0x400600E4 Access: Read-write Reset: See Table 28-7 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
28.15.9 SMC Write Protect Status Register Name: SMC_WPSR Address: 0x400600E8 Type: Read-only Value: See Table 28-7 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register.
29. Clock Generator 29.1 Description The Clock Generator user interface is embedded within the Power Management Controller and is described in Section 30.17 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 29.
29.3 Block Diagram Figure 29-1.
29.4 Slow Clock The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The slow clock is generated either by the slow clock crystal oscillator or by the slow clock RC oscillator.
29.4.1 Slow Clock RC Oscillator By default, the slow clock RC oscillator is enabled and selected. The user has to take into account the possible drifts of the RC oscillator. More details are given in the section “DC Characteristics” of the product datasheet. It can be disabled via the XTALSEL bit in SUPC_CR.
29.4.2 Slow Clock Crystal Oscillator The Clock Generator integrates a 32768 Hz low-power oscillator. To use this oscillator, the XIN32 and XOUT32 pins must be connected to a 32768 Hz crystal. Two external capacitors must be wired as shown in Figure 29-2. More details are given in the section “DC Characteristics” of the product datasheet. Note that the user is not obliged to use the slow clock crystal and can use the RC oscillator instead. Figure 29-2.
29.5 Main Clock Figure 29-3 shows the main clock block diagram. Figure 29-3. Main Clock Block Diagram CKGR_MOR MOSCRCEN CKGR_MOR MOSCRCF PMC_SR MOSCRCS Fast RC Oscillator CKGR_MOR PMC_SR MOSCSEL MOSCSELS 0 CKGR_MOR MAINCK Main Clock MOSCXTEN 1 3-20 MHz Crystal or Ceramic Resonator Oscillator XIN XOUT CKGR_MOR MOSCXTST PMC_SR 3-20 MHz Oscillator Counter SLCK Slow Clock MOSCXTS CKGR_MOR MOSCRCEN CKGR_MOR CKGR_MCFR MOSCXTEN RCMEAS CKGR_MOR MOSCSEL CKGR_MCFR MAINCK Main Clock Ref.
29.5.1 Fast RC Oscillator After reset, the 4/8/12 MHz fast RC oscillator is enabled with the 4 MHz frequency selected and it is selected as the source of MAINCK. MAINCK is the default clock selected to start the system. The fast RC oscillator frequencies are calibrated in production except the lowest frequency which is not calibrated. Refer to the “DC Characteristics” section of the product datasheet.
29.5.2 Fast RC Oscillator Clock Frequency Adjustment It is possible for the user to adjust the main RC oscillator frequency through PMC_OCR. By default, SEL4/8/12 are low, so the RC oscillator will be driven with Flash calibration bits which are programmed during chip production. The user can adjust the trimming of the 4/8/12 MHz fast RC oscillator through this register in order to obtain more accurate frequency (to compensate derating factors such as temperature and voltage).
29.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator After reset, the 3 to 20 MHz crystal or ceramic resonator-based oscillator is disabled and it is not selected as the source of MAINCK. The user can select the 3 to 20 MHz crystal or ceramic resonator-based oscillator to be the source of MAINCK, as it provides a more accurate frequency. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCXTEN bit in CKGR_MOR.
29.5.4 Main Clock Oscillator Selection The user can select either the 4/8/12 MHz fast RC oscillator or the 3 to 20 MHz crystal or ceramic resonator-based oscillator to be the source of main clock. The advantage of the 4/8/12 MHz fast RC oscillator is that it provides fast start-up time, this is why it is selected by default (to start the system) and when entering wait mode. The advantage of the 3 to 20 MHz crystal or ceramic resonator-based oscillator is that it is very accurate.
29.5.5 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator Both sources must be enabled during the switchover operation. Only after completion can the unused oscillator be disabled. If switching to fast crystal oscillator, the clock presence must first be checked according to what is described in Section 29.5.6 ”Software Sequence to Detect the Presence of Fast Crystal” because the source may not be reliable (crystal failure or bypass on a non-existent clock).
29.5.6 Software Sequence to Detect the Presence of Fast Crystal The frequency meter carried on CKGR_MCFR is operating on the selected main clock and not on the fast crystal clock nor on the fast RC oscillator clock. Therefore, to check for the presence of the fast crystal clock, it is necessary to have the main clock (MAINCK) driven by the fast crystal clock (MOSCSEL=1).
29.5.7 Main Clock Frequency Counter The device features a main clock frequency counter that provides the frequency of the main clock. The main clock frequency counter is reset and starts incrementing at the main clock speed after the next rising edge of the slow clock in the following cases: When the 4/8/12 MHz fast RC oscillator clock is selected as the source of main clock and when this oscillator becomes stable (i.e.
29.6 Divider and PLL Block The device features one divider/one PLL block that permits a wide range of frequencies to be selected on either the master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the frequency of the main clock. Figure 29-4 shows the block diagram of the dividers and PLL blocks. Figure 29-4.
29.6.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLL (PLLA) allows multiplication of the divider’s outputs.
30. Power Management Controller (PMC) 30.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M4 processor. The Supply Controller selects between the 32 kHz RC oscillator or the slow crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized.
30.3 Block Diagram Figure 30-1.
Figure 30-2. Master Clock Controller PMC_MCKR PMC_MCKR CSS PRES SLCK Master Clock Prescaler MAINCK MCK PLLACK To the Processor Clock Controller (HCLK) 30.5 Processor Clock Controller The PMC features a Processor Clock Controller (HCLK) that implements the processor sleep mode. The processor clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup Mode Register (PMC_FSMR).
30.8 Peripheral Clock Controller The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral Clock Controller. The user can individually enable and disable the clock on the peripherals. The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1 (PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers.
The system enters wait mode either by setting the WAITMODE bit in CKGR_MOR, or by executing the WaitForEvent (WFE) instruction of the processor while the LPM bit is at 1 in PMC_FSMR. Immediately after setting the WAITMODE bit or using the WFE instruction, wait for the MCKRDY bit to be set in PMC_SR. A fast startup is enabled upon the detection of a programmed level on one of the 16 wake-up inputs (WKUP) or upon an active alarm from the RTC, RTT and USB Controller.
30.12 Startup from Embedded Flash The inherent start-up time of the embedded Flash cannot provide a fast startup of the system. If system fast start-up time is not required, the first instruction after a wait mode exit can be located in the embedded Flash. Under these conditions, prior to entering wait mode, the Flash controller must be programmed to perform access in 0 wait-state (see Flash controller section).
It takes 2 slow RC oscillator clock cycles to detect and switch from the main oscillator, to the fast RC oscillator if the source master clock (MCK) is main clock (MAINCK), or three slow clock RC oscillator cycles if the source of MCK is PLLACK. A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock failure is detected.
7. Select the master clock and processor clock The master clock and the processor clock are configurable via PMC_MCKR. The CSS field is used to select the clock source of the master clock and processor clock dividers. By default, the selected clock source is the main clock. The PRES field is used to define the processor clock and master clock prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64).
Once PMC_PCKx register has been configured, the corresponding programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by polling PCKRDYx in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (PCKRDYx) has been enabled in PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation.
30.15 Clock Switching Details 30.15.1 Master Clock Switching Timings Table 30-1 and give the worst case timings required for the master clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added. Table 30-1. Clock Switching Timings (Worst Case) Fro m Main Clock SLCK PLL Clock Main Clock – 4 x SLCK + 2.5 x Main Clock SLCK 0.
30.15.2 Clock Switching Waveforms Figure 30-6. Switch Master Clock from Slow Clock to PLLx Clock Slow Clock PLLx Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 30-7.
Figure 30-8. Change PLLx Programming Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Slow Clock Write CKGR_PLLxR Figure 30-9.
30.16 Register Write Protection To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “PMC Write Protection Mode Register” (PMC_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the “PMC Write Protection Status Register” (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
30.17 Power Management Controller (PMC) User Interface Table 30-2.
Table 30-2. Register Mapping (Continued) Offset Register Name 0x0110 Oscillator Calibration Register PMC_OCR Reserved – PLL Maximum Multiplier Value Register PMC_PMMR 0114 - 0x120 0x130 0134 - 0x144 Reserved – Note: If an offset is not listed in the table it must be considered as “reserved”.
30.17.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0x400E0400 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . UDP: USB Device Port Clock Enable 0: No effect. 1: Enables the 48 MHz clock (UDPCK) of the USB Device Port.
30.17.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0x400E0404 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . UDP: USB Device Port Clock Disable 0: No effect. 1: Disables the 48 MHz clock (UDPCK) of the USB Device Port.
30.17.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0x400E0408 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – UDP: USB Device Port Clock Status 0: The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1: The 48 MHz clock (UDPCK) of the USB Device Port is enabled.
30.17.4 PMC Peripheral Clock Enable Register 0 Name: PMC_PCER0 Address: 0x400E0410 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.5 PMC Peripheral Clock Disable Register 0 Name: PMC_PCDR0 Address: 0x400E0414 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.6 PMC Peripheral Clock Status Register 0 Name: PMC_PCSR0 Address: 0x400E0418 Access: Read-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 – 5 – 4 – 3 – 2 – 1 – 0 – PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled.
30.17.7 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0x400E0420 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 CFDEN 24 MOSCSEL 23 22 21 20 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 WAITMODE 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 5 MOSCRCF 4 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
MOSCRCF: Main On-Chip RC Oscillator Frequency Selection At startup, the main on-chip RC Oscillator frequency is 4 MHz. Value Name Description 0x0 4_MHz The Fast RC Oscillator Frequency is at 4 MHz (default) 0x1 8_MHz The Fast RC Oscillator Frequency is at 8 MHz 0x2 12_MHz The Fast RC Oscillator Frequency is at 12 MHz Note: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR register. Therefore MOSCRCF and MOSCRCEN cannot be changed at the same time.
30.17.8 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0x400E0424 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 RCMEAS 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.9 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0x400E0428 Access: Read/Write 31 – 30 – 29 ONE 28 – 27 – 26 25 MULA 24 23 22 21 20 19 18 17 16 10 9 8 2 1 0 MULA 15 – 14 – 13 7 6 5 12 11 PLLACOUNT 4 3 DIVA Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
30.17.10 PMC Master Clock Register Name: PMC_MCKR Address: 0x400E0430 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 PLLADIV2 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 – 1 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.11 PMC USB Clock Register Name: PMC_USB Address: 0x400E0438 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 – 0 – USBDIV 2 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • USBDIV: Divider for USB Clock USB Clock is Input clock divided by USBDIV+1.
30.17.12 PMC Programmable Clock Register Name: PMC_PCKx Address: 0x400E0440 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 1 CSS 0 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.
30.17.
30.17.15 PMC Status Register Name: PMC_SR Address: 0x400E0468 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 FOS 19 CFDS 18 CFDEV 17 MOSCRCS 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 OSCSELS 6 – 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS MOSCXTS: Main XTAL Oscillator Status 0: Main XTAL oscillator is not stabilized. 1: Main XTAL oscillator is stabilized.
CFDEV: Clock Failure Detector Event 0: No clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. 1: At least one clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. CFDS: Clock Failure Detector Status 0: A clock failure of the fast crystal oscillator clock is not detected. 1: A clock failure of the fast crystal oscillator clock is detected.
30.17.
30.17.17 PMC Fast Startup Mode Register Name: PMC_FSMR Address: 0x400E0470 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 LPM 19 – 18 USBAL 17 RTCAL 16 RTTAL 15 FSTT15 14 FSTT14 13 FSTT13 12 FSTT12 11 FSTT11 10 FSTT10 9 FSTT9 8 FSTT8 7 FSTT7 6 FSTT6 5 FSTT5 4 FSTT4 3 FSTT3 2 FSTT2 1 FSTT1 0 FSTT0 FLPM This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.18 PMC Fast Startup Polarity Register Name: PMC_FSPR Address: 0x400E0474 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 FSTP15 14 FSTP14 13 FSTP13 12 FSTP12 11 FSTP11 10 FSTP10 9 FSTP9 8 FSTP8 7 FSTP7 6 FSTP6 5 FSTP5 4 FSTP4 3 FSTP3 2 FSTP2 1 FSTP1 0 FSTP0 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.19 PMC Fault Output Clear Register Name: PMC_FOCR Address: 0x400E0478 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FOCLR FOCLR: Fault Output Clear Clears the clock failure detector fault output.
30.17.20 PMC Write Protection Mode Register Name: PMC_WPMR Address: 0x400E04E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). See Section 30.
30.17.21 PMC Write Protection Status Register Name: PMC_WPSR Address: 0x400E04E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PMC_WPSR. 1: A write protection violation has occurred since the last read of the PMC_WPSR.
30.17.22 PMC Peripheral Clock Enable Register 1 Name: PMC_PCER1 Address: 0x400E0500 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.23 PMC Peripheral Clock Disable Register 1 Name: PMC_PCDR1 Address: 0x400E0504 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
30.17.24 PMC Peripheral Clock Status Register 1 Name: PMC_PCSR1 Address: 0x400E0508 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled.
30.17.25 PMC Oscillator Calibration Register Name: PMC_OCR Address: 0x400E0510 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 SEL12 22 21 20 19 CAL12 18 17 16 15 SEL8 14 13 12 11 CAL8 10 9 8 7 SEL4 6 5 4 3 CAL4 2 1 0 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . CAL4: RC Oscillator Calibration bits for 4 MHz Calibration bits applied to the RC Oscillator when SEL4 is set.
30.17.26 PLL Maximum Multiplier Value Register Name: PMC_PMMR Address: 0x400E0530 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 PLLA_MMAX 8 7 6 5 4 3 2 1 0 PLLA_MMAX This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
31. Advanced Encryption Standard (AES) 31.1 Description The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-38 Recommendation.
31.3 Product Dependencies 31.3.1 Power Management The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to configure the PMC to enable the AES clock. 31.3.2 Interrupt The AES interface has an interrupt line connected to the Interrupt Controller. Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES. Table 31-1. 31.
In CTR mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after processing 1 megabyte of data. If the file to be processed is greater than 1 megabyte, this file must be split into fragments of 1 megabyte. Prior to loading the first fragment into AES_IDATARx, AES_IVRx must be fully programmed with the initial counter value.
When processing completes, the DATRDY flag in the AES Interrupt Status Register (AES_ISR) is raised. If an interrupt has been enabled by setting the DATRDY bit in the AES_IER, the interrupt line of the AES is activated. When the software reads one of the AES_ODATARx, the DATRDY bit is automatically cleared. 31.4.3.
31.4.4.1 Manual and Auto Modes If LOD = 0 The DATRDY flag is cleared when at least one of the AES_ODATARx is read (See Figure 31-1). Figure 31-1. Manual and Auto Modes with LOD = 0 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx register(s) (Auto mode) Read the AES_ODATARx DATRDY Encryption or Decryption Process If the user does not want to read the AES_ODATARx between each encryption/decryption, the DATRDY flag will not be cleared.
Figure 31-3. DMA transfer with LOD = 0 Enable DMA Channels associated to AES_IDATARx and AES_ODATARx Multiple Encryption or Decryption Processes Write accesses into AES_IDATARx BTC /channel 0 Read accesses into AES_ODATARx BTC /channel 1 Message fully processed (cipher or decipher) last block can be read If LOD = 1 This mode is recommended to process AES CBC-MAC operating mode.
31.5 Security Features 31.5.1 Unspecified Register Access Detection When an unspecified register access occurs, the URAD flag in the AES_ISR is raised. Its source is then reported in the Unspecified Register Access Type (URAT) field. Only the last unspecified register access is available through the URAT field.
31.6 Advanced Encryption Standard (AES) User Interface Table 31-5.
31.6.1 AES Control Register Name: AES_CR Address: 0x40004000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START START: Start Processing 0: No effect 1: Starts manual encryption/decryption process. SWRST: Software Reset 0: No effect. 1: Resets the AES.
31.6.2 AES Mode Register Name: AES_MR Address: 0x40004004 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 CKEY 15 – 14 13 LOD 12 6 5 10 9 KEYSIZE 4 PROCDLY 11 OPMOD 7 CFBS 8 SMOD 3 2 1 0 DUALBUFF – – CIPHER CIPHER: Processing Mode 0: Decrypts data. 1: Encrypts data. DUALBUFF: Dual Input Buffer Value Name Description 0x0 INACTIVE AES_IDATARx cannot be written during processing of previous block.
KEYSIZE: Key Size Value Name Description 0x0 AES128 AES Key Size is 128 bits 0x1 AES192 AES Key Size is 192 bits 0x2 AES256 AES Key Size is 256 bits Values which are not listed in the table must be considered as “reserved”.
CKEY: Key Value 0xE Name Description PASSWD This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE. Always reads as 0.
31.6.3 AES Interrupt Enable Register Name: AES_IER Address: 0x40004010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
31.6.4 AES Interrupt Disable Register Name: AES_IDR Address: 0x40004014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
31.6.5 AES Interrupt Mask Register Name: AES_IMR Address: 0x40004018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
31.6.6 AES Interrupt Status Register Name: AES_ISR Address: 0x4000401C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready 0: Output data not valid. 1: Encryption or decryption process is completed.
31.6.7 AES Key Word Register x Name: AES_KEYWRx Address: 0x40004020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEYW 23 22 21 20 KEYW 15 14 13 12 KEYW 7 6 5 4 KEYW KEYW: Key Word The four/six/eight 32-bit Key Word Registers set the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption. AES_KEYWR0 corresponds to the first word of the key and respectively AES_KEYWR3/AES_KEYWR5/AES_KEYWR7 to the last one.
31.6.8 AES Input Data Register x Name: AES_IDATARx Address: 0x40004040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA IDATA: Input Data Word The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption. AES_IDATAR0 corresponds to the first word of the data to be encrypted/decrypted, and AES_IDATAR3 to the last one.
31.6.9 AES Output Data Register x Name: AES_ODATARx Address: 0x40004050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted. AES_ODATAR0 corresponds to the first word, AES_ODATAR3 to the last one.
31.6.10 AES Initialization Vector Register x Name: AES_IVRx Address: 0x40004060 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV IV: Initialization Vector The four 32-bit Initialization Vector Registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input.
32. Chip Identifier (CHIPID) 32.1 Description Chip Identifier (CHIPID) registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
32.3 Chip Identifier (CHIPID) User Interface Table 32-2.
32.3.
Value Name Description 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved NVPSIZ2: Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 – Reserved 7 128K 128 Kbytes 8 – Reserved 9 256K 256 Kbytes 10 512K 512 Kbytes 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved SRAMSIZ: Internal SRAM S
Value Name Description 13 256K 256 Kbytes 14 96K 96 Kbytes 15 512K 512 Kbytes ARCH: Architecture Identifier Value Name Description 0x3C SAM4E SAM4E Series NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory ROM and Embedded Flash Memory 3 ROM_FLASH NVPSIZ is ROM size NVPSIZ2 is Flash size EXT: Extension Flag 0 = Chip ID has a single register defini
32.3.2 Chip ID Extension Register Name: CHIPID_EXID Address: 0x400E0744 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID EXID: Chip ID Extension Reads 0 if the EXT bit in CHIPID_CIDR is 0.
33. Controller Area Network (CAN) 33.1 Description The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/s. CAN controller accesses are made through configuration registers.
33.3 Block Diagram Figure 33-1.
33.4 Application Block Diagram Figure 33-2. 33.5 Application Block Diagram Layers Implementation CAN-based Profiles Software CAN-based Application Layer Software CAN Data Link Layer CAN Controller CAN Physical Layer Transceiver I/O Lines Description Table 33-1. I/O Lines Description Name Description Type CANRX CAN Receive Serial Data Input CANTX CAN Transmit Serial Data Output 33.6 Product Dependencies 33.6.
33.6.3 Interrupt The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the CAN interrupt requires the interrupt controller to be programmed first. Note that it is not recommended to use the CAN interrupt line in edge-sensitive mode. Table 33-3. 33.7 Peripheral IDs Instance ID CAN0 37 CAN1 38 CAN Controller Features 33.7.
Figure 33-3. Message Acceptance Procedure CAN_MAMx CAN_MIDx & Message Received & == No Message Refused Yes Message Accepted CAN_MFIDx If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx.
It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers. Several mailboxes can be chained to receive a buffer. They must be configured with the same ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow. Table 33-4.
33.7.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR).
Figure 33-4. Partition of the CAN Bit Time NOMINAL BIT TIME SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample Point SYNC SEG: SYNChronization Segment This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. It is one TQ long. PROP SEG: PROPagation Segment This part of the bit time is used to compensate for the physical delay times within the network.
t BIT = t CSC + t PRS + t PHS1 + t PHS2 The time quantum is calculated as follows: t CSC = ( BRP + 1 ) ⁄ t peripheral clock Note: The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized. t PRS = t CSC × ( PROPAG + 1 ) t PHS1 = t CSC × ( PHASE1 + 1 ) t PHS2 = t CSC × ( PHASE2 + 1 ) To compensate for phase shifts between clock oscillators of different controllers on the bus, the CAN controller must resynchronize on any relevant signal edge of the current transmission.
Example of bit timing determination for CAN baudrate of 500 Kbit/s: fPeripheral clock = 48 MHz CAN baudrate = 500 Kbit/s => bit time = 2 µs Delay of the bus driver: 50 ns Delay of the receiver: 30 ns Delay of the bus line (20 m): 110 ns The total number of time quanta in a bit time must be comprised between 8 and 25.
the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width. Figure 33-6.
one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an Error Frame transmission. Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are decremented upon correct transmissions or receptions, respectively.
The current CAN bus state can be determined by reading the TEC and REC fields of CAN_ECR. 33.7.4.3 Overload The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field respectively.
Figure 33-8. Enabling Low-power Mode Arbitration lost Mailbox 1 CAN BUS Mailbox 3 LPEN= 1 LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSR1) MRDY (CAN_MSR3) CAN_TIM 0x0 33.7.5.2 Disabling Low-power Mode The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller.
Figure 33-9. Disabling Low-power Mode Bus Activity Detected CAN BUS Message x Message lost LPM (CAN_MR) Interframe synchronization SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSRx) 33.8 Functional Description 33.8.1 CAN Controller Initialization After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller.
Figure 33-10. Possible Initialization Procedure Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (Interrupt Controller) Configure a Mailbox in Reception Mode Change CAN_BR value (ABM == 1 and CANEN == 1) Errors ? Yes (CAN_SR or CAN_MSRx) No ABM = 0 and CANEN = 0 CANEN = 1 (ABM == 0) End of Initialization 33.8.2 CAN Controller Interrupt Handling There are two different types of interrupts.
̶ ̶ Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over. Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register. All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR.
Receive with Overwrite Mailbox A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
Figure 33-13.
33.8.3.2 Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers.
Figure 33-15. Transmitting Messages MBx message CAN BUS MBx message MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Abort MBx message Try to Abort MBx message Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx 33.8.3.3 Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. Figure 33-16.
Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx.
case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR. Figure 33-18. Consumer Handling CAN BUS Remote Frame Message x Remote Frame Message y MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) (CAN_MDLx CAN_MDHx) Message y Message x 33.8.
33.8.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. Figure 33-20.
Figure 33-21.
33.8.5 Write Protected Registers To prevent any single software error that may corrupt CAN behavior, the registers listed below can be writeprotected by setting the WPEN bit in the CAN Write Protection Mode Register (CAN_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the CAN Write Protection Status Register (CAN_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
33.9 Controller Area Network (CAN) User Interface Table 33-6.
33.9.1 CAN Mode Register Name: CAN_MR Address: 0x40010000 (0), 0x40014000 (1) Access: Read-write 31 – 23 – 15 – 7 DRPT 30 – 22 – 14 – 6 TIMFRZ 29 – 21 – 13 – 5 TTM 28 – 20 – 12 – 4 TEOF 27 – 19 – 11 – 3 OVL 26 25 24 18 – 10 – 2 ABM 17 – 9 – 1 LPM 16 – 8 – 0 CANEN This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. CANEN: CAN Controller Enable 0: The CAN Controller is disabled. 1: The CAN Controller is enabled.
DRPT: Disable Repeat 0: When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1: When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
33.9.2 CAN Interrupt Enable Register Name: CAN_IER Address: 0x40010004 (0), 0x40014004 (1) Access: Write-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 MBx: Mailbox x Interrupt Enable 0: No effect. 1: Enable Mailbox x interrupt. ERRA: Error Active Mode Interrupt Enable 0: No effect. 1: Enable ERRA interrupt.
TSTP: TimeStamp Interrupt Enable 0: No effect. 1: Enable TSTP interrupt. CERR: CRC Error Interrupt Enable 0: No effect. 1: Enable CRC Error interrupt. SERR: Stuffing Error Interrupt Enable 0: No effect. 1: Enable Stuffing Error interrupt. AERR: Acknowledgment Error Interrupt Enable 0: No effect. 1: Enable Acknowledgment Error interrupt. FERR: Form Error Interrupt Enable 0: No effect. 1: Enable Form Error interrupt. BERR: Bit Error Interrupt Enable 0: No effect.
33.9.3 CAN Interrupt Disable Register Name: CAN_IDR Address: 0x40010008 (0), 0x40014008 (1) Access: Write-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 MBx: Mailbox x Interrupt Disable 0: No effect. 1: Disable Mailbox x interrupt. ERRA: Error Active Mode Interrupt Disable 0: No effect. 1: Disable ERRA interrupt.
TSTP: TimeStamp Interrupt Disable 0: No effect. 1: Disable TSTP interrupt. CERR: CRC Error Interrupt Disable 0: No effect. 1: Disable CRC Error interrupt. SERR: Stuffing Error Interrupt Disable 0: No effect. 1: Disable Stuffing Error interrupt. AERR: Acknowledgment Error Interrupt Disable 0: No effect. 1: Disable Acknowledgment Error interrupt. FERR: Form Error Interrupt Disable 0: No effect. 1: Disable Form Error interrupt. BERR: Bit Error Interrupt Disable 0: No effect.
33.9.4 CAN Interrupt Mask Register Name: CAN_IMR Address: 0x4001000C (0), 0x4001400C (1) Access: Read-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 MBx: Mailbox x Interrupt Mask 0: Mailbox x interrupt is disabled. 1: Mailbox x interrupt is enabled. ERRA: Error Active Mode Interrupt Mask 0: ERRA interrupt is disabled.
TSTP: Timestamp Interrupt Mask 0: TSTP interrupt is disabled. 1: TSTP interrupt is enabled. CERR: CRC Error Interrupt Mask 0: CRC Error interrupt is disabled. 1: CRC Error interrupt is enabled. SERR: Stuffing Error Interrupt Mask 0: Bit Stuffing Error interrupt is disabled. 1: Bit Stuffing Error interrupt is enabled. AERR: Acknowledgment Error Interrupt Mask 0: Acknowledgment Error interrupt is disabled. 1: Acknowledgment Error interrupt is enabled.
33.9.5 CAN Status Register Name: CAN_SR Address: 0x40010010 (0), 0x40014010 (1) Access: Read-only 31 OVLSY 23 TSTP 15 – 7 MB7 30 TBSY 22 TOVF 14 – 6 MB6 29 RBSY 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 MBx: Mailbox x Event 0: No event occurred on Mailbox x. 1: An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx.
This flag is set depending on TEC counter value. A node is in bus off state when TEC counter is greater than or equal to 256 (decimal). SLEEP: CAN controller in Low power Mode 0: CAN controller is not in low power mode. 1: CAN controller is in low power mode. This flag is automatically reset when Low power mode is disabled WAKEUP: CAN controller is not in Low power Mode 0: CAN controller is in low power mode. 1: CAN controller is not in low power mode.
FERR: Form Error 0: No form error occurred during a previous transfer 1: A form error occurred during a previous transfer A form error results from violations on one or more of the fixed form of the following bit fields: – CRC delimiter – ACK delimiter – End of frame – Error delimiter – Overload delimiter This flag is automatically cleared by reading CAN_SR. BERR: Bit Error 0: No bit error occurred during a previous transfer. 1: A bit error occurred during a previous transfer.
33.9.6 CAN Baudrate Register Name: CAN_BR Address: 0x40010014 (0), 0x40014014 (1) Access: Read-write 31 – 23 – 15 – 7 – 30 – 22 29 – 21 14 – 6 13 28 – 20 12 SJW 5 PHASE1 4 27 – 19 BRP 11 – 3 – 26 – 18 25 – 17 24 SMP 16 10 9 PROPAG 1 PHASE2 8 2 0 This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. Any modification on one of the fields of the CAN_BR must be done while CAN module is disabled.
33.9.7 CAN Timer Register Name: CAN_TIM Address: 0x40010018 (0), 0x40014018 (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 TIMER TIMER TIMER: Timer This field represents the internal CAN controller 16-bit timer value.
33.9.8 CAN Timestamp Register Name: CAN_TIMESTP Address: 0x4001001C (0), 0x4001401C (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 7 6 5 28 27 – – 20 19 – – 12 11 MTIMESTAMP 4 3 MTIMESTAMP 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 MTIMESTAMP: Timestamp This field carries the value of the internal CAN controller 16-bit timer value at the start or end of frame.
33.9.9 CAN Error Counter Register Name: CAN_ECR Address: 0x40010020 (0), 0x40014020 (1) Access: Read-only 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 24 TEC 16 11 – 3 10 – 2 9 – 1 8 – 0 TEC 15 – 7 14 – 6 13 – 5 12 – 4 REC REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG.
33.9.10 CAN Transfer Command Register Name: CAN_TCR Address: 0x40010024 (0), 0x40014024 (1) Access: Write-only 31 TIMRST 23 – 15 – 7 MB7 30 – 22 – 14 – 6 MB6 29 – 21 – 13 – 5 MB5 28 – 20 – 12 – 4 MB4 27 – 19 – 11 – 3 MB3 26 – 18 – 10 – 2 MB2 25 – 17 – 9 – 1 MB1 24 – 16 – 8 – 0 MB0 This register initializes several transfer requests at the same time. MBx: Transfer Request for Mailbox x Mailbox Object Type Description Receive It receives the next message.
33.9.11 CAN Abort Command Register Name: CAN_ACR Address: 0x40010028 (0), 0x40014028 (1) Access: Write-only 31 – 23 – 15 – 7 MB7 30 – 22 – 14 – 6 MB6 29 – 21 – 13 – 5 MB5 28 – 20 – 12 – 4 MB4 27 – 19 – 11 – 3 MB3 26 – 18 – 10 – 2 MB2 25 – 17 – 9 – 1 MB1 24 – 16 – 8 – 0 MB0 This register initializes several abort requests at the same time.
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33.9.13 CAN Write Protection Status Register Name: CAN_WPSR Address: 0x400100E8 (0), 0x400140E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS WPVS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of the CAN_WPSR.
33.9.14 CAN Message Mode Register Name: CAN_MMRx [x=0..
33.9.15 CAN Message Acceptance Mask Register Name: CAN_MAMx [x=0..
33.9.16 CAN Message ID Register Name: CAN_MIDx [x=0..
33.9.17 CAN Message Family ID Register Name: CAN_MFIDx [x=0..
33.9.18 CAN Message Status Register Name: CAN_MSRx [x=0..
MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0: Previous transfer is not aborted. 1: Previous transfer has been aborted. This flag is cleared by writing to CAN_MCRx Mailbox Object Type Description Receive Reserved Receive with overwrite Reserved Transmit Previous transfer has been aborted Consumer The remote frame transfer request has been aborted. Producer The response to the remote frame transfer has been aborted.
Cleared by reading the CAN_MSRx. Mailbox Object Type Description Receive Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message. Receive with overwrite Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost.
33.9.19 CAN Message Data Low Register Name: CAN_MDLx [x=0..
33.9.20 CAN Message Data High Register Name: CAN_MDHx [x=0..
33.9.21 CAN Message Control Register Name: CAN_MCRx [x=0..
MACR: Abort Request for Mailbox x Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Cancels transfer request if the message has not been transmitted to the CAN transceiver. Consumer Cancels the current transfer before the remote frame has been sent. Producer Cancels the current transfer. The next remote frame will not be serviced. It is possible to set the MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR.
34. Parallel Input/Output Controller (PIO) 34.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface.
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34.3 Block Diagram Figure 34-1. Block Diagram PIODCCLK Data PDC Status PIODC[7:0] Parallel Capture Mode PIODCEN1 PIODCEN2 Interrupt Controller PMC PIO Interrupt Peripheral Clock PIO Controller Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Up to 32 peripheral IOs Embedded Peripheral PIN 31 APB Table 34-1.
Figure 34-2.
34.4 Product Dependencies 34.4.1 Pin Multiplexing Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e.
34.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 34-3. In this description each signal shown represents one of up to 32 possible indexes. Figure 34-3.
registers results in setting or clearing the corresponding bit in the Pull-down Status register (PIO_PPDSR). Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled. Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible.
34.5.4 Output Control When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable register (PIO_OER) and Output Disable register (PIO_ODR).
Figure 34-4. Output Line Timings Peripheral clock Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 34.5.8 Inputs The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral.
The glitch filters are controlled by the Input Filter Enable register (PIO_IFER), the Input Filter Disable register (PIO_IFDR) and the Input Filter Status register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals.
These additional modes are: Rising edge detection Falling edge detection Low-level detection High-level detection In order to select an additional interrupt mode: The type of event detection (edge or level) must be selected by writing in the Edge Select register (PIO_ESR) and Level Select register (PIO_LSR) which select, respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR).
Figure 34-7.
Figure 34-8. Input Change Interrupt Timings When No Additional Interrupt Modes Peripheral clock Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 34.5.11 I/O Lines Lock When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of this peripheral via an input of the PIO Controller.
Figure 34-9. Programmable I/O Delays PIO PAin[0] PAout[0] Programmable Delay Line DELAY1 PAin[1] PAout[1] Programmable Delay Line DELAY2 PAin[2] PAout[2] Programmable Delay Line DELAYx 34.5.13 Programmable Schmitt Trigger It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the Schmitt trigger is requested when using the QTouch™ Library. 34.5.14 Parallel Capture Mode 34.5.14.
the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multiplexing table(s) in the section “Package and Pinout”. Once enabled, the parallel capture mode samples the data at rising edge of the sensor clock and resynchronizes it with the peripheral clock domain. The size of the data which can be read in PIO_PCRHR can be programmed using the DSIZE field in PIO_PCMR.
Figure 34-12. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 1, HALFS = 0) Peripheral clock PIODCCLK PIODC[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR 0x3423_1201 RDATA (PIO_PCRHR) 0x7867_5645 Figure 34-13.
Figure 34-14. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRSTS = 1) Peripheral clock PIODCCLK PIODC[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR RDATA (PIO_PCRHR) 0x7856_3412 34.5.14.3 Restrictions Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR can be changed ONLY if the parallel capture mode is disabled at this time (PCEN = 0 in PIO_PCMR).
8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the parallel capture mode WITHOUT changing the previous configuration. 34.5.15 I/O Lines Programming Example The programming example shown in Table 34-3 is used to obtain the following configuration.
34.5.16 Register Write Protection To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status Register (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
34.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Table 34-4.
Table 34-4.
Table 34-4. Register Mapping (Continued) Offset Register Name Access Reset 0x160 Parallel Capture Interrupt Status Register PIO_PCISR Read-only 0x00000000 0x164 Parallel Capture Reception Holding Register PIO_PCRHR Read-only 0x00000000 0x0168–0x018C Reserved for PDC Registers – – – Notes: 1. Reset value depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines.
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34.6.6 PIO Output Status Register Name: PIO_OSR Address: 0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x400E1218 (PIOC), 0x400E1418 (PIOD), 0x400E1618 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Status 0: The I/O line is a pure input.
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34.6.10 PIO Set Output Data Register Name: PIO_SODR Address: 0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x400E1230 (PIOC), 0x400E1430 (PIOD), 0x400E1630 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Set Output Data 0: No effect.
34.6.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC), 0x400E1434 (PIOD), 0x400E1634 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Clear Output Data 0: No effect.
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34.6.13 PIO Pin Data Status Register Name: PIO_PDSR Address: (PIOE) 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC), 0x400E143C (PIOD), 0x400E163C Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Data Status 0: The I/O line is at level 0.
34.6.14 PIO Interrupt Enable Register Name: PIO_IER Address: 0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x400E1240 (PIOC), 0x400E1440 (PIOD), 0x400E1640 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Enable 0: No effect.
34.6.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC), 0x400E1444 (PIOD), 0x400E1644 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Disable 0: No effect.
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34.6.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
34.6.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. P0–P31: Peripheral Select.
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34.6.29 PIO Slow Clock Divider Debouncing Register Name: PIO_SCDR Address: (PIOE) 0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC), 0x400E148C (PIOD), 0x400E168C Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – 7 6 2 1 0 DIV 5 4 3 DIV DIV: Slow Clock Divider Selection for Debouncing tdiv_slclk = 2 × (DIV + 1) × tslow_clock.
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34.6.39 PIO Edge Select Register Name: PIO_ESR Address: (PIOE) 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC), 0x400E14C0 (PIOD), 0x400E16C0 Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Edge Interrupt Selection 0: No effect.
34.6.40 PIO Level Select Register Name: PIO_LSR Address: (PIOE) 0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x400E12C4 (PIOC), 0x400E14C4 (PIOD), 0x400E16C4 Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Level Interrupt Selection 0: No effect.
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34.6.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC), 0x400E14E0 (PIOD), 0x400E16E0 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Lock Status 0: The I/O line is not locked.
34.6.46 PIO Write Protection Mode Register Name: PIO_WPMR Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC), 0x400E14E4 (PIOD), 0x400E16E4 (PIOE) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 – – 5 – 4 – – – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
34.6.47 PIO Write Protection Status Register Name: PIO_WPSR Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC), 0x400E14E8 (PIOD), 0x400E16E8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PIO_WPSR.
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34.6.49 PIO I/O Delay Register Name: PIO_DELAYR Address: 0x400E0F10 (PIOA), 0x400E1110 (PIOB), 0x400E1310 (PIOC), 0x400E1510 (PIOD), 0x400E1710 (PIOE) Access: Read/Write 31 30 29 28 27 26 Delay7 23 22 21 20 19 18 Delay5 15 14 13 6 12 11 17 16 10 9 8 1 0 Delay2 5 4 3 Delay1 24 Delay4 Delay3 7 25 Delay6 2 Delay0 Delayx [x=0..7]: Delay Control for Simultaneous Switch Reduction Gives the number of elements in the delay line associated to pad x.
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34.6.55 PIO Parallel Capture Reception Holding Register Name: PIO_PCRHR Address: 0x400E0F64 (PIOA), 0x400E1164 (PIOB), 0x400E1364 (PIOC), 0x400E1564 (PIOD), 0x400E1764 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDATA 23 22 21 20 RDATA 15 14 13 12 RDATA 7 6 5 4 RDATA RDATA: Parallel Capture Mode Reception Data. if DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful.
35. Serial Peripheral Interface (SPI) 35.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a Shift register that serially transmits data bits to other SPIs.
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35.3 Block Diagram Figure 35-1. Block Diagram AHB Matrix DMA Bus clock Peripheral bridge PMC 790 Peripheral clock SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 SPI Trig.
35.4 Application Block Diagram Figure 35-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 MISO NC Slave 1 MOSI NPCS3 NSS SPCK MISO Slave 2 MOSI NSS 35.5 Signal Description Table 35-1. Signal Description Type 35.
Table 35-2. I/O Lines (Continued) SPI NPCS1 PA9 B SPI NPCS1 PA31 A SPI NPCS1 PB14 A SPI NPCS1 PC4 B SPI NPCS2 PA10 B SPI NPCS2 PA30 B SPI NPCS2 PB2 B SPI NPCS3 PA3 B SPI NPCS3 PA5 B SPI NPCS3 PA22 B SPI SPCK PA14 A 35.6.2 Power Management The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. 35.6.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master mode. 35.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled.
Figure 35-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 5 7 6 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) * Not defined. 35.7.3 Master Mode Operations When configured in Master mode, the SPI operates on the clock generated by the internal programmable baud rate generator.
If the SPI_RDR has not been read before new data is received, the Overrun Error (OVRES) bit in the SPI_SR is set. As long as this flag is set, data is loaded in the SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 35-5, shows a block diagram of the SPI when operating in Master mode. Figure 35-6 on page 796 shows a flow chart describing how transfers are handled. 35.7.3.1 Master Mode Block Diagram Figure 35-5.
35.7.3.2 Master Mode Flow Diagram Figure 35-6.
Figure 35-7 shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags within the SPI_SR during an 8-bit data transfer in Fixed mode without the PDC or DMA involved. Figure 35-7.
Figure 35-8 shows the behavior of Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags within the SPI_SR during an 8-bit data transfer in Fixed mode with the Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data. The next pointer and counter are not used. The RDRF and TDRE are not shown because these flags are managed by the PDC when using the PDC. Figure 35-8.
Delay between consecutive transfers—independently programmable for each chip select by writing the DLYBCT field. The time required by the SPI slave device to process received data is managed through DLYBCT. This time depends on the SPI slave system activity. These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 35-9. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 35.7.3.
The variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the SPI_MR. Data written in the SPI_TDR is 32 bits wide and defines the real data to be transmitted and the destination peripheral. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on the NPCS lines of either SPI_MR or SPI_TDR (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e., all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has four Chip Select registers. As a result, when external decoding is activated, each NPCS chip select defines the characteristics of up to four peripherals.
remains active. To de-assert the chip select line at the end of the transfer, the Last Transfer (LASTXFER) bit in the SPI_MR must be set to 1 before writing the last data to transmit into the SPI_TDR. 35.7.3.10 Peripheral Deselection with DMA or PDC DMA or PDC provides faster reloads of the SPI_TDR compared to software. However, depending on the system activity, it is not guaranteed that the SPI_TDR is written with the next data before the end of the current transfer.
Figure 35-11. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..n] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..n] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..n] DLYBCT DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..
35.7.4 SPI Slave Mode When operating in Slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits until NSS goes active before receiving the serial clock from an external master. When NSS falls, the clock is validated and the data is loaded in the SPI_RDR depending on the BITS field configured in the SPI_CSR0. These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in the SPI_CSR0.
35.7.5 Register Write Protection To prevent any single software error from corrupting SPI behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the SPI Write Protection Status Register (SPI_WPSR) is set and the WPVSRC field indicates the register in which the write access has been attempted.
35.8 Serial Peripheral Interface (SPI) User Interface Table 35-5.
35.8.1 SPI Control Register Name: SPI_CR Address: 0x40088000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI.
35.8.2 SPI Mode Register Name: SPI_MR Address: 0x40088004 Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register. MSTR: Master/Slave Mode 0: SPI is in Slave mode. 1: SPI is in Master mode.
1: Local loopback path enabled. LLB controls the local loopback on the data shift register for testing in Master mode only (MISO is internally connected on MOSI). PCS: Peripheral Chip Select This field is only used if fixed peripheral select is active (PS = 0).
35.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0x40088008 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD RD: Receive Data Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero.
35.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0x4008800C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
35.8.5 SPI Status Register Name: SPI_SR Address: 0x40088010 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – SPIENS 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF RDRF: Receive Data Register Full 0: No data has been received since the last read of SPI_RDR.
TXBUFE: TX Buffer Empty 0: SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1: Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. NSSR: NSS Rising 0: No rising edge detected on NSS pin since the last read. 1: A rising edge occurred on NSS pin since the last read. TXEMPTY: Transmission Registers Empty 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay.
35.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0x40088014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
35.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0x40088018 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
35.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0x4008801C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled.
35.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Address: 0x40088030 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT CSNAAT NCPHA CPOL This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register. Note: SPI_CSRx registers must be written even if the user wants to use the default reset values.
BITS: Bits Per Transfer (See the note below the register bitmap.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
35.8.10 SPI Write Protection Mode Register Name: SPI_WPMR Address: 0x400880E4 Access: Read/Write Reset: See Table 35-5. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN WPEN: Write Protection Enable 0: Disables the Write Protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII) 1: Enables the Write Protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII) See Section 35.7.
35.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0x400880E8 Access: Read-only Reset: See Table 35-5 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS WPVS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of SPI_WPSR.
36. Two-wire Interface (TWI) 36.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
36.3 List of Abbreviations Table 36-2. 36.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 36-1.
36.5 Application Block Diagram Figure 36-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull-up value as given by the I²C Standard 36.5.1 I/O Lines Description Table 36-3. 36.6 I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output Product Dependencies 36.6.
36.6.3 Interrupt The TWI interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TWI. Table 36-5. 36.7 Peripheral IDs Instance ID TWI0 17 TWI1 18 Functional Description 36.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 36-4).
36.7.3 Master Mode 36.7.3.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 36.7.3.2 Application Block Diagram Figure 36-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull-up value as given by the I²C Standard 36.7.3.
Figure 36-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 36-7.
Figure 36-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 36.7.3.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7bit slave address to notify the slave device.
Figure 36-9. Master Read with One Data Byte TWD S DADR R A DATA NA P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 36-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) P NA TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read Figure 36-11.
address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 36-13. See Figure 36-12 and Figure 36-14 for Master Write operation with internal address. The three internal address bytes are configurable through the Master Mode Register (TWI_MMR). If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be set to 0.
1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 36-14 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 36-14.
36.7.3.8 SMBus Quick Command (Master Mode Only) The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. Figure 36-15. SMBus Quick Command TWD S DADR R/W A P TXCOMP TXRDY Write QUICK command in TWI_CR 36.7.3.
Figure 36-16.
Figure 36-17.
Figure 36-18.
Figure 36-19.
Figure 36-20.
Figure 36-21.
36.7.4 Multi-master Mode 36.7.4.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
Figure 36-22. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 36-23.
Figure 36-24.
36.7.5 Slave Mode 36.7.5.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 36.7.5.2 Application Block Diagram Figure 36-25.
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 36-27 on page 844.
The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 36-27 describes the Write operation.
Clock Synchronization in Read Mode The clock is tied low if the internal shifter is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the internal shifter is loaded. Figure 36-29 describes the clock synchronization in Read mode. Figure 36-29.
Figure 36-30. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full S TWD SADR W A DATA0 A DATA1 TWI_RHR A NA DATA2 DATA1 DATA0 is not read in the RHR S ADR DATA2 SCLWS SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD As soon as a START is detected TXCOMP Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2.
Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command. Figure 36-32 describes the repeated start + reversal from Write to Read mode. Figure 36-32. Repeated Start + Reversal from Write to Read Mode DATA2 TWI_THR S TWD SADR W A DATA0 A TWI_RHR DATA1 DATA0 A Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY Read TWI_RHR EOSACC TXCOMP Notes: Cleared after read As soon as a START is detected 1.
Figure 36-33. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? GACC = 1 ? No No EOSACC = 1 ? No SVREAD = 0 ? TXRDY= 1 ? No No Write in TWI_THR No TXCOMP = 1 ? RXRDY= 0 ? No END Read TWI_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR 36.7.
36.8 Two-wire Interface (TWI) User Interface Table 36-7.
36.8.1 TWI Control Register Name: TWI_CR Address: 0x400A8000 (0), 0x400AC000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.
SVEN: TWI Slave Mode Enabled 0: No effect. 1: Enables the slave mode (SVDIS must be written to 0) Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. QUICK: SMBus Quick Command 0: No effect.
36.8.
36.8.3 TWI Slave Mode Register Name: TWI_SMR Address: 0x400A8008 (0), 0x400AC008 (1) Access: Read/Write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the TWI Write Protection Mode Register.
36.8.4 TWI Internal Address Register Name: TWI_IADR Address: 0x400A800C (0), 0x400AC00C (1) Access: Read/Write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
36.8.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0x400A8010 (0), 0x400AC010 (1) Access: Read/Write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV This register can only be written if the WPEN bit is cleared in the TWI Write Protection Mode Register. TWI_CWGR is only used in Master mode.
36.8.6 TWI Status Register Name: TWI_SR Address: 0x400A8020 (0), 0x400AC020 (1) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame.
1: It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 36-26 on page 843, Figure 36-29 on page 845, Figure 36-31 on page 846 and Figure 36-32 on page 847. SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode.
ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
36.8.7 TWI Interrupt Enable Register Name: TWI_IER Address: 0x400A8024 (0), 0x400AC024 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
36.8.8 TWI Interrupt Disable Register Name: TWI_IDR Address: 0x400A8028 (0), 0x400AC028 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
36.8.9 TWI Interrupt Mask Register Name: TWI_IMR Address: 0x400A802C (0), 0x400AC02C (1) Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled.
36.8.
36.8.
36.8.12 TWI Write Protection Mode Register Name: TWI_WPMR Address: 0x400A80E4 (0), 0x400AC0E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x545749 (“TWI” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x545749 (“TWI” in ASCII). See Section 36.7.
36.8.13 TWI Write Protection Status Register Name: TWI_WPSR Address: 0x400A80E8 (0), 0x400AC0E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 23 22 21 20 WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the TWI_WPSR. 1: A write protection violation has occurred since the last read of the TWI_WPSR.
37. Universal Asynchronous Receiver Transmitter (UART) 37.1 Description The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with a peripheral DMA controller (PDC) permits packet handling for these tasks with processor time reduced to a minimum. 37.2 Embedded Characteristics 37.
37.4 Product Dependencies 37.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Controller to enable I/O line operations of the UART. Table 37-2. I/O Lines Instance Signal I/O Line Peripheral UART0 URXD0 PA9 A UART0 UTXD0 PA10 A UART1 URXD1 PA5 C UART1 UTXD1 PA6 C 37.4.2 Power Management The UART clock can be controlled through the Power Management Controller (PMC).
Figure 37-2. Baud Rate Generator CD CD 16-bit Counter peripheral clock OUT >1 Divide by 16 1 0 Baud Rate Clock 0 Receiver Sampling Clock 37.5.2 Receiver 37.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the Control Register (UART_CR) with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
Figure 37-4. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period URXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 37.5.2.3 Receiver Ready When a complete character is received, it is transferred to the Receive Holding Register (UART_RHR) and the RXRDY status bit in the Status Register (UART_SR) is set. The bit RXRDY is automatically cleared when UART_RHR is read. Figure 37-5.
Figure 37-7. Parity Error S URXD D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 37.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the Control Register (UART_CR) is written with the bit RSTSTA at 1.
Figure 37-9. Character Transmission Example: Parity enabled Baud Rate Clock UTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 37.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in UART_SR. The transmission starts when the programmer writes in the UART_THR, and after the written character is transferred from UART_THR to the internal shift register. The TXRDY bit remains high until a second character is written in UART_THR.
37.5.5 Register Write Protection To prevent any single software error from corrupting UART behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the UART Write Protection Mode Register (UART_WPMR). The following registers can be write-protected: UART Mode Register UART Baud Rate Generator Register 37.5.6 Test Modes The UART supports three test modes. These modes of operation are programmed by using the CHMODE field in UART_MR.
37.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 37-3.
37.6.1 UART Control Register Name: UART_CR Address: 0x400E0600 (0), 0x40060600 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
37.6.
37.6.3 UART Interrupt Enable Register Name: UART_IER Address: 0x400E0608 (0), 0x40060608 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
37.6.4 UART Interrupt Disable Register Name: UART_IDR Address: 0x400E060C (0), 0x4006060C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
37.6.5 UART Interrupt Mask Register Name: UART_IMR Address: 0x400E0610 (0), 0x40060610 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled.
37.6.6 UART Status Register Name: UART_SR Address: 0x400E0614 (0), 0x40060614 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY RXRDY: Receiver Ready 0: No character has been received since the last read of the UART_RHR, or the receiver is disabled.
TXEMPTY: Transmitter Empty 0: There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1: There are no characters in UART_THR and there are no characters being processed by the transmitter. TXBUFE: Transmission Buffer Empty 0: The buffer empty signal from the transmitter PDC channel is inactive. 1: The buffer empty signal from the transmitter PDC channel is active.
37.6.7 UART Receiver Holding Register Name: UART_RHR Address: 0x400E0618 (0), 0x40060618 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last received character if RXRDY is set.
37.6.8 UART Transmit Holding Register Name: UART_THR Address: 0x400E061C (0), 0x4006061C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
37.6.
37.6.10 UART Write Protection Mode Register Name: UART_WPMR Address: 0x400E06E4 (0), 0x400606E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x554152 (UART in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x554152 (UART in ASCII). See Section 37.5.
38. Universal Synchronous Asynchronous Receiver Transmitter (USART) 38.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
38.3 Block Diagram Figure 38-1. USART Block Diagram Interrupt Controller USART Interrupt PIO Controller USART RXD Receiver Channel RTS (Peripheral) DMA Controller TXD Channel Transmitter CTS DTR Modem Signals Control Bus clock DCD Bridge APB PMC 886 RI User Interface Baud Rate Generator Peripheral clock Table 38-1.
38.4 Application Block Diagram Figure 38-2.
38.5 I/O Lines Description Table 38-2.
38.6 Product Dependencies 38.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
38.7 Functional Description 38.7.1 Baud Rate Generator The baud rate generator provides the bit period clock, also named the baud rate clock, to both the receiver and the transmitter.
Baud Rate Calculation Example Table 38-5 shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 38-5. Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (Bit/s) Calculation Result CD Actual Baud Rate (Bit/s) Error 3,686,400 38,400 6.00 6 38,400.00 0.00% 4,915,200 38,400 8.00 8 38,400.00 0.00% 5,000,000 38,400 8.14 8 39,062.50 1.
SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 – Over ) CD + FP ------- 8 The modified architecture is presented below: Figure 38-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 3 Glitch-free Logic 1 0 FIDI >1 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 Sampling Clock 38.7.1.
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 38-6. Table 38-6. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 38-7. Table 38-7.
38.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the US_CR. However, the transmitter registers can be programmed before being enabled. The receiver and the transmitter can be enabled together or independently.
Figure 38-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 38.7.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1.
Figure 38-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register.
Figure 38-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. A hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e., respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur.
to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 3814. The sample pulse rejection mechanism applies. The RXIDLEV bit in the US_MAN informs the USART of the receiver line idle state value (receiver line inactive). The user must define RXIDLEV to ensure reliable synchronization.
Figure 38-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported.
The USART peripheral is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 38-18 for an example of ASK modulation scheme.
Figure 38-20. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 38.7.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the RXRDY bit in US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one.
Table 38-9 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 38-9.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard register (US_TTGR). When this field is written to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 38-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard.
with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in US_CSR rises. Then, the user can either: Stop the counter clock until a new character is received. This is performed by writing a one to the STTTO (Start Time-out) bit the US_CR. In this case, the idle state on RXD before a new character is received will not provide a time-out.
38.7.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of US_CSR. The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing US_CR with the RSTSTA bit to 1. Figure 38-25.
Figure 38-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 38.7.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR.
Figure 38-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 38-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 38-29.
receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. 38.7.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in US_CSR. If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing US_CR with the RSTIT bit to 1.
38.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kb/s, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 38-12. Table 38-12. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 µs 9.6 Kb/s 19.53 µs 19.2 Kb/s 9.77 µs 38.4 Kb/s 4.88 µs 57.6 Kb/s 3.26 µs 115.2 Kb/s 1.63 µs Figure 38-34 shows an example of character transmission. Figure 38-34.
Table 38-13. IrDA Baud Rate Error (Continued) Peripheral Clock Baud Rate (Bit/s) CD Baud Rate Error Pulse Time (µs) 20,000,000 19,200 65 0.16% 9.77 32,768,000 19,200 107 0.31% 9.77 40,000,000 19,200 130 0.16% 9.77 3,686,400 9,600 24 0.00% 19.53 20,000,000 9,600 130 0.16% 19.53 32,768,000 9,600 213 0.16% 19.53 40,000,000 9,600 260 0.16% 19.53 3,686,400 2,400 96 0.00% 78.13 20,000,000 2,400 521 0.03% 78.13 32,768,000 2,400 853 0.04% 78.13 38.7.5.
Figure 38-36. Typical Connection to a RS485 Bus USART RXD Differential Bus TXD RTS The USART is set in RS485 mode by writing the value 0x1 to the USART_MODE field in US_MR. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 38-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 38-37.
38.7.7 Modem Mode The USART features Modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in Modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in Modem mode is performed by writing the USART_MODE field in US_MR to the value 0x3.
38.7.8 SPI Mode The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
If the divided peripheral clock is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the SCK pin, this value can be odd if the peripheral clock is selected. In SPI Slave mode: The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR. Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART SCK pin.
Figure 38-38. SPI Transfer Format (CPHA = 1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS Figure 38-39.
transmission (even if US_THR has been written) while the receiver side is not ready (character not read). When WRDBT equals 0, the character is transmitted whatever the receiver status. If WRDBT is set to 1, the transmitter waits for the Receive Holding register (US_RHR) to be read before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side.
Figure 38-40. Normal Mode Configuration RXD Receiver TXD Transmitter 38.7.9.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 38-41. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 38-41. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 38.7.9.
38.7.10 Register Write Protection To prevent any single software error from corrupting USART behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “USART Write Protection Mode Register” (US_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the “USART Write Protection Status Register” (US_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
38.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 38-16.
38.8.1 USART Control Register Name: US_CR Address: 0x400A0000 (0), 0x400A4000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see “USART Control Register (SPI_MODE)” on page 925. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.
RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1.
38.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0x400A0000 (0), 0x400A4000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 927. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.
RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits OVRE, UNRE in US_CSR. FCS: Force SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect. 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI slave devices supporting the CSAAT mode (Chip Select Active After Transfer). RCS: Release SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect.
38.8.3 USART Mode Register Name: US_MR Address: 0x400A0004 (0), 0x400A4004 (1) Access: Read/Write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955.
CHRL: Character Length Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits SYNC: Synchronous Mode Select 0: USART operates in asynchronous mode. 1: USART operates in synchronous mode.
CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. OVER: Oversampling Mode 0: 16 × Oversampling. 1: 8 × Oversampling. INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Start frame delimiter is one bit. 38.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0x400A0004 (0), 0x400A4004 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 – 18 – 17 – 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 6 5 4 3 2 1 0 7 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 927.
CHMODE: Channel Mode Value Name Description 0 NORMAL Normal mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic echo mode. Receiver input is connected to the TXD pin. Local loopback mode. Transmitter output is connected to the Receiver Input. Remote loopback mode. RXD pin is internally connected to the TXD pin. CPOL: SPI Clock Polarity Applicable if USART operates in SPI mode (slave or master, USART_MODE = 0xE or 0xF): 0: The inactive state value of SPCK is logic level zero.
38.8.5 USART Interrupt Enable Register Name: US_IER Address: 0x400A0008 (0), 0x400A4008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 934.
DSRIC: Data Set Ready Input Change Enable DCDIC: Data Carrier Detect Input Change Interrupt Enable CTSIC: Clear to Send Input Change Interrupt Enable MANE: Manchester Error Interrupt Enable SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 933
38.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0x400A0008 (0), 0x400A4008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 927.
38.8.7 USART Interrupt Disable Register Name: US_IDR Address: 0x400A000C (0), 0x400A400C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 937.
DSRIC: Data Set Ready Input Change Disable DCDIC: Data Carrier Detect Input Change Interrupt Disable CTSIC: Clear to Send Input Change Interrupt Disable MANE: Manchester Error Interrupt Disable 936 SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
38.8.8 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0x400A000C (0), 0x400A400C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 927.
38.8.9 USART Interrupt Mask Register Name: US_IMR Address: 0x400A0010 (0), 0x400A4010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” on page 940.
DSRIC: Data Set Ready Input Change Mask DCDIC: Data Carrier Detect Input Change Interrupt Mask CTSIC: Clear to Send Input Change Interrupt Mask MANE: Manchester Error Interrupt Mask SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 939
38.8.10 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0x400A0010 (0), 0x400A4010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 927.
38.8.11 USART Channel Status Register Name: US_CSR Address: 0x400A0014 (0), 0x400A4014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 944.
1: At least one stop bit has been detected low since the last RSTSTA. PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
RI: Image of RI Input 0: RI is set to 0. 1: RI is set to 1. DSR: Image of DSR Input 0: DSR is set to 0 1: DSR is set to 1. DCD: Image of DCD Input 0: DCD is set to 0. 1: DCD is set to 1. CTS: Image of CTS Input 0: CTS is set to 0. 1: CTS is set to 1. MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA.
38.8.12 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0x400A0014 (0), 0x400A4014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 927.
38.8.13 USART Receive Holding Register Name: US_RHR Address: 0x400A0018 (0), 0x400A4018 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last character received if RXRDY is set. RXSYNH: Received Sync 0: Last character received is a data. 1: Last character received is a command.
38.8.14 USART Transmit Holding Register Name: US_THR Address: 0x400A001C (0), 0x400A401C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. TXSYNH: Sync Field to be Transmitted 0: The next character sent is encoded as a data.
38.8.15 USART Baud Rate Generator Register Name: US_BRGR Address: 0x400A0020 (0), 0x400A4020 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955.
38.8.16 USART Receiver Time-out Register Name: US_RTOR Address: 0x400A0024 (0), 0x400A4024 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955. TO: Time-out Value 0: The receiver time-out is disabled.
38.8.17 USART Transmitter Timeguard Register Name: US_TTGR Address: 0x400A0028 (0), 0x400A4028 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955. • TG: Timeguard Value 0: The transmitter timeguard is disabled.
38.8.18 USART FI DI RATIO Register Name: US_FIDI Address: 0x400A0040 (0), 0x400A4040 (1) Access: Read/Write Reset: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955.
38.8.19 USART Number of Errors Register Name: US_NER Address: 0x400A0044 (0), 0x400A4044 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE = 0x4 or 0x6 in “USART Mode Register” on page 927. NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer.
38.8.20 USART IrDA FILTER Register Name: US_IF Address: 0x400A004C (0), 0x400A404C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE = 0x8 in “USART Mode Register” on page 927. This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955.
38.8.21 USART Manchester Configuration Register Name: US_MAN Address: 0x400A0050 (0), 0x400A4050 (1) Access: Read/Write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 17 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955.
01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s RX_MPOL: Receiver Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register.
38.8.22 USART Write Protection Mode Register Name: US_WPMR Address: 0x400A00E4 (0), 0x400A40E4 (1) Access: Read/Write Reset: See Table 38-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII).
38.8.23 USART Write Protection Status Register Name: US_WPSR Address: 0x400A00E8 (0), 0x400A40E8 (1) Access: Read-only Reset: See Table 38-16 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the US_WPSR.
39. Timer Counter (TC) 39.1 Description The Timer Counter (TC) includes nine identical 32-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
̶ ̶ 39.3 Two multi-purpose input/output signals acting as trigger event Trigger/capture events can be directly synchronized by PWM signals Internal interrupt signal Two global registers that act on all TC channels Read of the Capture registers by the PDC Compare event fault generation for PWM Register Write Protection Block Diagram Figure 39-1.
Table 39-2. Signal Name Description XC0, XC1, XC2 Channel Signal TIOA Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT SYNC 39.4 Interrupt Signal Output (internal signal) Synchronization Input Signal (from configuration register) Pin Name List Table 39-3. 39.
Table 39-4. I/O Lines TC1 TIOB4 PC27 B TC1 TIOB5 PC30 B TC2 TCLK6 PC7 B TC2 TCLK7 PC10 B TC2 TCLK8 PC14 B TC2 TIOA6 PC5 B TC2 TIOA7 PC8 B TC2 TIOA8 PC11 B TC2 TIOB6 PC6 B TC2 TIOB7 PC9 B TC2 TIOB8 PC12 B 39.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. 39.5.3 Interrupt The TC has an interrupt line connected to the Interrupt Controller (IC).
39.6.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC Block Mode Register (TC_BMR). See Figure 39-2 “Clock Chaining Selection”.
Figure 39-3. Clock Selection TCCLKS CLKI TIMER_CLOCK1 Synchronous Edge Detection TIMER_CLOCK2 TIMER_CLOCK3 Selected Clock TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 Peripheral Clock BURST 1 39.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 39-4. 962 • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC Channel Control Register (TC_CCR).
Figure 39-4. Clock Control Selected Clock Trigger CLKSTA CLKEN Q Q CLKDIS S R S R Stop Event Counter Clock Disable Event 39.6.5 TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs.
39.6.7 Capture Operating Mode This mode is entered by clearing the WAVE bit in the TC_CMR. Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 39-6 shows the configuration of the TC channel when programmed in Capture Mode. 39.6.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers.
Figure 39-5. Example of Transfer with PDC ETRGEDG = 1, LDRA = 1, LDRB = 2, ABETRG = 0, TIOB TIOA RA RB Peripheral trigger Transfer to System Memory RA RB RA RB T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (tmin = 8 peripheral clocks) ETRGEDG = 3, LDRA = 3, LDRB = 0, ABETRG = 0 TIOB TIOA RA Peripheral trigger Transfer to System Memory RA RA RA RA T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (tmin = 8 peripheral clocks) 39.6.
SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 MTIOA MTIOB 1 BURST ABETRG CLKI SWTRG If RA is not loaded or RB is Loaded Edge Detector ETRGEDG Peripheral Clock Synchronous Edge Detection R S OVF LDRB Edge Detector Edge Detector Edge Subsampler SBSMPLR Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG Counter RESET Trig CLK Q Q CLKSTA Compare RC = Register C Timer/Counter Channel LDBDIS Capture Register B CLKDIS TC1_SR TIOA
39.6.11 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST TCCLKS ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG Peripheral Clock Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWT
39.6.12.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 232-1. Once 232-1 has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 39-8. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 39-9. RC Compare cannot be programmed to generate a trigger in this configuration.
39.6.12.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 39-10. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 39-11.
39.6.12.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 232-1. Once 232-1 is reached, the value of TC_CV is decremented to 0, then re-incremented to 232-1 and so on. See Figure 39-12. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 39-13.
39.6.12.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 39-14. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 39-15.
39.6.13 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
Figure 39-16. Synchronization with PWM Timer/Counter TC_EMR0.TRIGSRCA Timer/Counter Channel 0 TIOA0 TIOA0 1 TC_EMR0.TRIGSRCB TIOB0 TIOB0 1 TC_EMR1.TRIGSRCA Timer/Counter Channel 1 TIOA1 TIOA1 1 TC_EMR1.TRIGSRCB TIOB1 TIOB1 1 TC_EMR2.TRIGSRCA Timer/Counter Channel 2 TIOA2 TIOA2 1 TC_EMR2.TRIGSRCB TIOB2 TIOB2 1 PWM comparator outputs (internal signals) respectively source of PWMH/L[2:0] 39.6.
The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 39.6.16 Quadrature Decoder Logic 39.6.16.1 Description The quadrature decoder logic is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of channel 0 and 1.
Figure 39-17. Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA Timer/Counter Channel 0 TIOA0 QDEN PHEdges 1 TIOB 1 XC0 TIOB0 TIOA0 PHA TIOB0 PHB TIOB1 IDX XC0 Speed/Position QDEN Index 1 TIOB TIOB1 1 XC0 Timer/Counter Channel 1 XC0 Rotation Direction Timer/Counter Channel 2 Speed Time Base 39.6.16.
Figure 39-18. Input Stage Input Pre-Processing MAXFILT SWAP 1 PHA Filter TIOA0 MAXFILT > 0 1 PHedge Direction and Edge Detection INVA 1 PHB Filter TIOB0 1 DIR 1 IDX INVB 1 1 IDX Filter TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interference.
Figure 39-19.
39.6.16.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the two quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
predefined value is configurable and corresponds to (MAXFILT + 1) * tperipheral clock ns. After being filtered there is no reason to have two edges closer than (MAXFILT + 1) * tperipheral clock ns under normal mode of operation. Figure 39-21.
39.6.16.5 Speed Measurement When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0. A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOA output.
This does not substitute the measurements of the number of pulses between two index pulses (if available) but provides a complementary method to detect damaged quadrature devices. 39.6.17 2-bit Gray Up/Down Counter for Stepper Motor Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA, TIOB outputs by means of the GCEN bit in TC_SMMRx. Up or Down count can be defined by writing bit DOWN in TC_SMMRx.
Figure 39-24.
39.7 Timer Counter (TC) User Interface Table 39-5.
39.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0x40090000 (0)[0], 0x40090040 (0)[1], 0x40090080 (0)[2], 0x40094000 (1)[0], 0x40094040 (1)[1], 0x40094080 (1)[2], 0x40098000 (2)[0], 0x40098040 (2)[1], 0x40098080 (2)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN • CLKEN: Counter Clock Enable Command 0: No effect.
39.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
• LDBSTOP: Counter Clock Stopped with RB Loading 0: Counter clock is not stopped when RB loading occurs. 1: Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal.
• SBSMPLR: Loading Edge Subsampling Ratio 988 Value Name Description 0 ONE Load a Capture Register each selected edge 1 HALF Load a Capture Register every 2 selected edges 2 FOURTH Load a Capture Register every 4 selected edges 3 EIGHTH Load a Capture Register every 8 selected edges 4 SIXTEENTH Load a Capture Register every 16 selected edges SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
39.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..2] (WAVE = 1) Access: Read/Write 31 30 29 BSWTRG 23 28 27 BEEVT 22 20 19 AEEVT 15 WAVE 14 13 7 CPCDIS 6 CPCSTOP WAVSEL 25 24 BCPC 21 ASWTRG 26 BCPB 18 17 16 ACPC 12 ENETRG 11 4 3 CLKI 5 BURST ACPA 10 9 EEVT 8 EEVTEDG 2 1 TCCLKS 0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event.
• ACPA: RA Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • B
• BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB 992 Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
39.7.4 TC Stepper Motor Mode Register Name: TC_SMMRx [x=0..
39.7.5 TC Register AB Name: TC_RABx [x=0..2] Address: 0x4009000C (0)[0], 0x4009004C (0)[1], 0x4009008C (0)[2], 0x4009400C (1)[0], 0x4009404C (1)[1], 0x4009408C (1)[2], 0x4009800C (2)[0], 0x4009804C (2)[1], 0x4009808C (2)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RAB 23 22 21 20 RAB 15 14 13 12 RAB 7 6 5 4 RAB • RAB: Register A or Register B RAB contains the next unread capture Register A or Register B value in real time.
39.7.6 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0x40090010 (0)[0], 0x40090050 (0)[1], 0x40090090 (0)[2], 0x40094010 (1)[0], 0x40094050 (1)[1], 0x40094090 (1)[2], 0x40098010 (2)[0], 0x40098050 (2)[1], 0x40098090 (2)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
39.7.7 TC Register A Name: TC_RAx [x=0..2] Address: 0x40090014 (0)[0], 0x40090054 (0)[1], 0x40090094 (0)[2], 0x40094014 (1)[0], 0x40094054 (1)[1], 0x40094094 (1)[2], 0x40098014 (2)[0], 0x40098054 (2)[1], 0x40098094 (2)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
39.7.8 TC Register B Name: TC_RBx [x=0..2] Address: 0x40090018 (0)[0], 0x40090058 (0)[1], 0x40090098 (0)[2], 0x40094018 (1)[0], 0x40094058 (1)[1], 0x40094098 (1)[2], 0x40098018 (2)[0], 0x40098058 (2)[1], 0x40098098 (2)[2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RB 23 22 21 20 RB 15 14 13 12 RB 7 6 5 4 RB This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
39.7.9 TC Register C Name: TC_RCx [x=0..2] Address: 0x4009001C (0)[0], 0x4009005C (0)[1], 0x4009009C (0)[2], 0x4009401C (1)[0], 0x4009405C (1)[1], 0x4009409C (1)[2], 0x4009801C (2)[0], 0x4009805C (2)[1], 0x4009809C (2)[2] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
39.7.10 TC Status Register Name: TC_SRx [x=0..
• ETRGS: External Trigger Status 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. • ENDRX: End of Receiver Transfer 0: The Receive End of Transfer signal from the PDC channel is inactive. 1: The Receive End of Transfer signal from the PDC channel is active. • RXBUFF: Reception Buffer Full 0: The Receive Buffer Full signal from the PDC channel is inactive.
39.7.11 TC Interrupt Enable Register Name: TC_IERx [x=0..
0: No effect. 1: Enables the External Trigger Interrupt. • ENDRX: End of Receiver Transfer 0: No effect. 1: Enables the PDC Receive End of Transfer Interrupt. • RXBUFF: Reception Buffer Full 0: No effect. 1: Enables the PDC Receive Buffer Full Interrupt.
39.7.12 TC Interrupt Disable Register Name: TC_IDRx [x=0..
0: No effect. 1: Disables the External Trigger Interrupt. • ENDRX: End of Receiver Transfer 0: No effect. 1: Disables the PDC Receive End of Transfer Interrupt. • RXBUFF: Reception Buffer Full 0: No effect. 1: Disables the PDC Receive Buffer Full Interrupt.
39.7.13 TC Interrupt Mask Register Name: TC_IMRx [x=0..
0: The External Trigger Interrupt is disabled. 1: The External Trigger Interrupt is enabled. • ENDRX: End of Receiver Transfer 0: The PDC Receive End of Transfer Interrupt is disabled. 1: The PDC Receive End of Transfer Interrupt is enabled. • RXBUFF: Reception Buffer Full 0: The PDC Receive Buffer Full Interrupt is disabled. 1: The PDC Receive Buffer Full Interrupt is enabled.
39.7.14 TC Extended Mode Register Name: TC_EMRx [x=0..
39.7.15 TC Block Control Register Name: TC_BCR Address: 0x400900C0 (0), 0x400940C0 (1), 0x400980C0 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
39.7.16 TC Block Mode Register Name: TC_BMR Address: 0x400900C4 (0), 0x400940C4 (1), 0x400980C4 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 23 22 21 20 19 – 18 AUTOC 17 IDXPHB 16 SWAP 12 EDGPHA 11 QDTRANS 10 SPEEDEN 9 POSEN 8 QDEN 4 3 2 1 0 MAXFILT 15 INVIDX 14 INVB 13 INVA 7 – 6 – 5 TC2XC2S 24 MAXFILT TC1XC1S TC0XC0S This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• POSEN: Position Enabled 0: Disable position. 1: Enables the position measure on channel 0 and 1. • SPEEDEN: Speed Enabled 0: Disabled. 1: Enables the speed measure on channel 0, the time base being provided by channel 2. • QDTRANS: Quadrature Decoding Transparent 0: Full quadrature decoding logic is active (direction change detected). 1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
39.7.17 TC QDEC Interrupt Enable Register Name: TC_QIER Address: 0x400900C8 (0), 0x400940C8 (1), 0x400980C8 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No effect. 1: Enables the interrupt when a rising edge occurs on IDX input. • DIRCHG: Direction Change 0: No effect.
39.7.18 TC QDEC Interrupt Disable Register Name: TC_QIDR Address: 0x400900CC (0), 0x400940CC (1), 0x400980CC (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No effect. 1: Disables the interrupt when a rising edge occurs on IDX input. • DIRCHG: Direction Change 0: No effect.
39.7.19 TC QDEC Interrupt Mask Register Name: TC_QIMR Address: 0x400900D0 (0), 0x400940D0 (1), 0x400980D0 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: The interrupt on IDX input is disabled. 1: The interrupt on IDX input is enabled. • DIRCHG: Direction Change 0: The interrupt on rotation direction change is disabled.
39.7.20 TC QDEC Interrupt Status Register Name: TC_QISR Address: 0x400900D4 (0), 0x400940D4 (1), 0x400980D4 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 DIR 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No Index input change since the last read of TC_QISR. 1: The IDX input has changed since the last read of TC_QISR.
39.7.21 TC Fault Mode Register Name: TC_FMR Address: 0x400900D8 (0), 0x400940D8 (1), 0x400980D8 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 ENCF1 0 ENCF0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
39.7.22 TC Write Protection Mode Register Name: TC_WPMR Address: 0x400900E4 (0), 0x400940E4 (1), 0x400980E4 (2) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). See Section 39.6.
40. Pulse Width Modulation Controller (PWM) 40.1 Description The PWM macrocell controls 4 channels independently. Each channel controls two complementary square output waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of the clocks provided by the clock generator.
40.
40.3 Block Diagram Figure 40-1.
40.5 Product Dependencies 40.5.1 I/O Lines The pins used for interfacing the PWM are multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Table 40-2.
Table 40-2. I/O Lines PWM PWML1 PA20 B PWM PWML1 PB12 A PWM PWML1 PC1 B PWM PWML1 PC15 B PWM PWML1 PD25 A PWM PWML2 PA16 C PWM PWML2 PA30 A PWM PWML2 PB13 A PWM PWML2 PC2 B PWM PWML2 PD26 A PWM PWML3 PA15 C PWM PWML3 PC3 B PWM PWML3 PC22 B PWM PWML3 PD27 A 40.5.2 Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM.
Table 40-4. Fault Inputs (Continued) Fault Generator External PWM Fault Input Number Polarity Level(1) Fault Input ID PXyy PWMFI2 User-defined 4 PXyy PWMFI3 User-defined 5 PXyy PWMFI4 User-defined 6 PXyy Note: PWMFI5 1. FPOL field in PWMC_FMR.
40.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. Clocked by the peripheral clock, the clock generator module provides 13 clocks. Each channel can independently choose one of the clock generator outputs. Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 40.6.1 PWM Clock Generator Figure 40-2.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to ‘0’. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except the peripheral clock. This situation is also true when the PWM peripheral clock is turned off through the Power Management Controller. CAUTION: Before using the PWM macrocell, the programmer must first enable the peripheral clock in the Power Management Controller (PMC). 40.6.
40.6.2.2 Comparator The comparator continuously compares its counter value with the channel period defined by CPRD in the PWM Channel Period Register (PWM_CPRDx) and the duty-cycle defined by CDTY in the PWM Channel Duty Cycle Register (PWM_CDTYx) to generate an output signal OCx accordingly. The different properties of the waveform of the output OCx are: the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator described in the previous section.
the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL bit of the PWM_CMRx. By default the signal starts by a low level. the waveform alignment. The output waveform can be left or center-aligned. Center-aligned waveforms can be used to generate non-overlapped waveforms. This property is defined in the CALG bit of the PWM_CMRx. The default mode is left-aligned. Figure 40-4.
Figure 40-5.
Up or down count mode can be configured on-the-fly by means of PWM_SMMR configuration registers. When GCEN0 is set to ‘1’, channels 0 and 1 outputs are driven with gray counter. Figure 40-6. 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 40.6.2.4 Dead-Time Generator The dead-time generator uses the comparator output OCx to provide the two complementary outputs DTOHx and DTOLx, which allows the PWM macrocell to drive external power control switches safely.
Figure 40-7. Complementary Output Waveforms Output waveform OCx CPOLx = 0 Output waveform DTOHx DTHIx = 0 Output waveform DTOLx DTLIx = 0 Output waveform DTOHx DTHIx = 1 Output waveform DTOLx DTLIx = 1 DTHx DTLx DTHx DTLx Output waveform OCx CPOLx = 1 Output waveform DTOHx DTHIx = 0 Output waveform DTOLx DTLIx = 0 Output waveform DTOHx DTHIx = 1 Output waveform DTOLx DTLIx = 1 40.6.2.
Figure 40-8. Override Output Selection DTOHx 0 OOOHx OOVHx 1 OSHx DTOLx 0 OOOLx OOVLx 1 OSLx The fields OSHx and OSLx in the PWM Output Selection Register (PWM_OS) allow the outputs of the dead-time generator DTOHx and DTOLx to be overridden by the value defined in the fields OOVHx and OOVLx in the PWM Output Override Value Register (PWM_OOV).
The polarity level of the fault inputs is configured by the FPOL field in the PWM Fault Mode Register (PWM_FMR). For fault inputs coming from internal peripherals such as ADC, Timer Counter, to name but a few, the polarity level must be FPOL = 1. For fault inputs coming from external GPIO pins the polarity level depends on the user's implementation. The configuration of the Fault Activation Mode (FMOD field in PWMC_FMR) depends on the peripheral generating the fault.
40.6.2.7 Spread Spectrum Counter The PWM macrocell includes a spread spectrum counter allowing the generation of a constantly varying duty cycle on the output PWM waveform (only for the channel 0). This feature may be useful to minimize electromagnetic interference or to reduce the acoustic noise of a PWM driven motor. This is achieved by varying the effective period in a range defined by a spread spectrum value which is programmed by the field SPRD in the PWM Spread Spectrum Register (PWM_SSPR).
one to the bit CPOLINVUP in the same register. In this case the polarity will be inverted synchronously with the PWM period and the bit CPOLUP is not taken into account. By inverting the polarity at a precise moment of the PWM period: Write the field ADEDGV and the field ADEDGM in the PWM Channel Additional Edge Register. As soon as the channel counter reaches the value defined by ADEDGV, the polarity of the output waveform is inverted.
The synchronous channels are defined by the SYNCx bits in the PWM Sync Channels Mode Register (PWM_SCM). Only one group of synchronous channels is allowed. When a channel is defined as a synchronous channel, the channel 0 is automatically defined as a synchronous channel too, because the channel 0 counter configuration is used by all the synchronous channels.
Table 40-6.
Figure 40-12. Method 1 (UPDM = 0) CCNT0 CDTYUPD 0x20 0x40 0x20 0x40 0x60 UPDULOCK CDTY 0x60 Method 2: Manual write of duty-cycle values and automatic trigger of the update In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period value must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD).
9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD). 10. The update of these registers will occur at the next PWM period of the synchronous channels when the Update Period is elapsed. Go to Step 8. for new values. Figure 40-13.
ENDTX (not relevant if DMA is used): this flag is set to ‘1’ when a PDC transfer is completed TXBUFE (not relevant if DMA is used): this flag is set to ‘1’ when the PDC buffer is empty (no pending PDC transfers) UNRE: this flag is set to ‘1’ when the update period defined by the UPR field has elapsed while the whole data has not been written by the PDC or DMA. It is reset to ‘0’ when the PWM_ISR2 is read.
Figure 40-15. Method 3 (UPDM = 2 and PTRM = 1 and PTRCS = 0) CCNT0 CDTYUPD 0x20 UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x20 0x60 0x40 0x80 0xB0 0xA0 0x3 0x3 0x1 0x0 0x40 0x1 0x0 0x1 0x60 0x0 0x1 0x80 0x2 0x3 0x0 0x1 0x2 0xA0 CMP0 match transfer request WRDY 40.6.2.
40.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 40.6.2.9 “Synchronous Channels”). These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, see Section 40.6.
is triggered. The comparison x update period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register. CAUTION: The write of PWM_CMPVUPDx must be followed by a write of PWM_CMPMUPDx. The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not masked. These interrupts can be enabled by the PWM Interrupt Enable Register 2 and disabled by the PWM Interrupt Disable Register 2.
Figure 40-18. Event Line Block Diagram CMPM0 (PWM_ISR2) CSEL0 (PWM_ELMRx) CMPM1 (PWM_ISR2) CSEL1 (PWM_ELMRx) CMPM2 (PWM_ISR2) CSEL2 (PWM_ELMRx) PULSE GENERATOR Event Line x CMPM7 (PWM_ISR2) CSEL7 (PWM_ELMRx) 40.6.5 PWM Controller Operations 40.6.5.1 Initialization Before enabling the channels, they must be configured by the software application as described below: 1042 Unlock User Interface by writing the WPCMD field in the PWM_WPCR.
40.6.5.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the PWM Channel Period Register (PWM_CPRDx) and the PWM Channel Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
Figure 40-19. Synchronized Period, Duty-Cycle and Dead-Time Update User's Writing User's Writing User's Writing PWM_DTUPDx Value PWM_CPRDUPDx Value PWM_CDTYUPDx Value PWM_CPRDx PWM_DTx PWM_CDTYx - If Asynchronous Channel -> End of PWM period - If Synchronous Channel -> End of PWM period and UPDULOCK = 1 - If Asynchronous Channel -> End of PWM period - If Synchronous Channel - If UPDM = 0 -> End of PWM period and UPDULOCK = 1 - If UPDM = 1 or 2 -> End of PWM period and end of Update Period 40.6.5.
Figure 40-20. Synchronized Update of Update Period Value of Synchronous Channels User's Writing PWM_SCUPUPD Value PWM_SCUP End of PWM period and end of update period of synchronous channels 40.6.5.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see Section 40.6.3 “PWM Comparison Units”).
Figure 40-21. Synchronized Update of Comparison Values and Configurations User's Writing User's Writing PWM_CMPVUPDx Value Comparison value for comparison x PWM_CMPMUPDx Value Comparison configuration for comparison x PWM_CMPVx PWM_CMPMx End of channel0 PWM period and end of comparison update period and and PWM_CMPMx written End of channel0 PWM period and end of comparison update period 40.6.5.
Register group 3: ̶ PWM Spread Spectrum Register ̶ PWM Spread Spectrum Update Register ̶ PWM Channel Period Register ̶ PWM Channel Period Update Register Register group 4: ̶ PWM Channel Dead Time Register ̶ PWM Channel Dead Time Update Register Register group 5: ̶ PWM Fault Mode Register ̶ PWM Fault Protection Value Register 1 There are two types of write protection: SW write protection—can be enabled or disabled by software HW write protection—can be enabled by software but only
40.7 Pulse Width Modulation Controller (PWM) User Interface Table 40-7.
Table 40-7.
Table 40-7.
40.7.1 PWM Clock Register Name: PWM_CLK Address: 0x40000000 Access: Read/Write 31 – 30 – 29 – 28 – 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 PREB DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the PWM Write Protection Status Register.
40.7.2 PWM Enable Register Name: PWM_ENA Address: 0x40000004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Channel ID 0: No effect. 1: Enable PWM output for channel x.
40.7.3 PWM Disable Register Name: PWM_DIS Address: 0x40000008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register. CHIDx: Channel ID 0: No effect. 1: Disable PWM output for channel x.
40.7.4 PWM Status Register Name: PWM_SR Address: 0x4000000C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Channel ID 0: PWM output for channel x is disabled. 1: PWM output for channel x is enabled.
40.7.
40.7.
40.7.
40.7.8 PWM Interrupt Status Register 1 Name: PWM_ISR1 Address: 0x4000001C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Counter Event on Channel x 0: No new counter event has occurred since the last read of the PWM_ISR1. 1: At least one counter event has occurred since the last read of the PWM_ISR1.
40.7.9 PWM Sync Channels Mode Register Name: PWM_SCM Address: 0x40000020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register. SYNCx: Synchronous Channel x 0: Channel x is not a synchronous channel. 1: Channel x is a synchronous channel.
40.7.10 PWM DMA Register Name: PWM_DMAR Address: 0x40000024 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 DMADUTY 15 14 13 12 DMADUTY 7 6 5 4 DMADUTY Only the first 16 bits (channel counter size) are significant. DMADUTY: Duty-Cycle Holding Register for DMA Access Each write access to PWM_DMAR sequentially updates the CDTY field of PWM_CDTYx with DMADUTY (only for channel configured as synchronous).
40.7.
40.7.12 PWM Sync Channels Update Period Register Name: PWM_SCUP Address: 0x4000002C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UPRCNT UPR UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register).
40.7.13 PWM Sync Channels Update Period Update Register Name: PWM_SCUPUPD Address: 0x40000030 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels.
40.7.
40.7.
40.7.
40.7.17 PWM Interrupt Status Register 2 Name: PWM_ISR2 Address: 0x40000040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY WRDY: Write Ready for Synchronous Channels Update 0: New duty-cycle and dead-time values for the synchronous channels cannot be written.
40.7.18 PWM Output Override Value Register Name: PWM_OOV Address: 0x40000044 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OOVL3 18 OOVL2 17 OOVL1 16 OOVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OOVH3 2 OOVH2 1 OOVH1 0 OOVH0 OOVHx: Output Override Value for PWMH output of the channel x 0: Override value is 0 for PWMH output of channel x. 1: Override value is 1 for PWMH output of channel x.
40.7.19 PWM Output Selection Register Name: PWM_OS Address: 0x40000048 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSL3 18 OSL2 17 OSL1 16 OSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSH3 2 OSH2 1 OSH1 0 OSH0 OSHx: Output Selection for PWMH output of the channel x 0: Dead-time generator output DTOHx selected as PWMH output of channel x. 1: Output override value OOVHx selected as PWMH output of channel x.
40.7.20 PWM Output Selection Set Register Name: PWM_OSS Address: 0x4000004C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSL3 18 OSSL2 17 OSSL1 16 OSSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSH3 2 OSSH2 1 OSSH1 0 OSSH0 OSSHx: Output Selection Set for PWMH output of the channel x 0: No effect. 1: Output override value OOVHx selected as PWMH output of channel x.
40.7.21 PWM Output Selection Clear Register Name: PWM_OSC Address: 0x40000050 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCL3 18 OSCL2 17 OSCL1 16 OSCL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCH3 2 OSCH2 1 OSCH1 0 OSCH0 OSCHx: Output Selection Clear for PWMH output of the channel x 0: No effect. 1: Dead-time generator output DTOHx selected as PWMH output of channel x.
40.7.22 PWM Output Selection Set Update Register Name: PWM_OSSUPD Address: 0x40000054 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSUPL3 18 OSSUPL2 17 OSSUPL1 16 OSSUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSUPH3 2 OSSUPH2 1 OSSUPH1 0 OSSUPH0 OSSUPHx: Output Selection Set for PWMH output of the channel x 0: No effect.
40.7.23 PWM Output Selection Clear Update Register Name: PWM_OSCUPD Address: 0x40000058 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCUPL3 18 OSCUPL2 17 OSCUPL1 16 OSCUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCUPH3 2 OSCUPH2 1 OSCUPH1 0 OSCUPH0 OSCUPHx: Output Selection Clear for PWMH output of the channel x 0: No effect.
40.7.24 PWM Fault Mode Register Name: PWM_FMR Address: 0x4000005C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 FFIL 15 14 13 12 FMOD 7 6 5 4 FPOL This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. FPOL: Fault Polarity For each field bit y (fault input number): 0: The fault y becomes active when the fault input y is at 0.
40.7.25 PWM Fault Status Register Name: PWM_FSR Address: 0x40000060 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 FS 7 6 5 4 FIV FIV: Fault Input Value For each field bit y (fault input number): 0: The current sampled value of the fault input y is 0 (after filtering if enabled). 1: The current sampled value of the fault input y is 1 (after filtering if enabled).
40.7.26 PWM Fault Clear Register Name: PWM_FCR Address: 0x40000064 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 FCLR FCLR: Fault Clear For each field bit y (fault input number): 0: No effect.
40.7.27 PWM Fault Protection Value Register 1 Name: PWM_FPV1 Address: 0x40000068 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPVL3 18 FPVL2 17 FPVL1 16 FPVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPVH3 2 FPVH2 1 FPVH1 0 FPVH0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register.
40.7.28 PWM Fault Protection Enable Register Name: PWM_FPE Address: 0x4000006C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. Only the first 8 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant.
40.7.29 PWM Event Line x Register Name: PWM_ELMRx Address: 0x4000007C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CSEL7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0 CSELy: Comparison y Selection 0: A pulse is not generated on the event line x when the comparison y matches. 1: A pulse is generated on the event line x when the comparison y match.
40.7.30 PWM Spread Spectrum Register Name: PWM_SSPR Address: 0x400000A0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 SPRDM 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 SPRD 15 14 13 12 SPRD 7 6 5 4 SPRD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. Only the first 16 bits (channel counter size) are significant.
40.7.31 PWM Spread Spectrum Update Register Name: PWM_SSPUP Address: 0x400000A4 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 SPRDUP 15 14 13 12 SPRDUP 7 6 5 4 SPRDUP This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the SPRD value.
40.7.32 PWM Stepper Motor Mode Register Name: PWM_SMMR Address: 0x400000B0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 DOWN1 16 DOWN0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 GCEN1 0 GCEN0 GCENx: Gray Count ENable 0: Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1] 1: Enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.
40.7.33 PWM Fault Protection Value Register 2 Name: PWM_FPV2 Address: 0x400000C0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPZL3 18 FPZL2 17 FPZL1 16 FPZL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPZH3 2 FPZH2 1 FPZH1 0 FPZH0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register.
40.7.34 PWM Write Protection Control Register Name: PWM_WPCR Address: 0x400000E4 Access: Write-only Reset: See Table 40-7 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WPRG1 2 WPRG0 1 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 WPRG5 6 WPRG4 5 WPRG3 4 WPRG2 0 WPCMD See Section 40.6.6 “Register Write Protection” for the list of registers that can be write-protected.
40.7.35 PWM Write Protection Status Register Name: PWM_WPSR Address: 0x400000E8 Access: Read-only Reset: See Table 40-7 31 30 29 28 27 26 25 24 19 18 17 16 WPVSRC 23 22 21 20 WPVSRC 15 – 14 – 13 WPHWS5 12 WPHWS4 11 WPHWS3 10 WPHWS2 9 WPHWS1 8 WPHWS0 7 WPVS 6 – 5 WPSWS5 4 WPSWS4 3 WPSWS3 2 WPSWS2 1 WPSWS1 0 WPSWS0 WPSWSx: Write Protect SW Status 0: The SW write protection x of the register group x is disabled.
40.7.36 PWM Comparison x Value Register Name: PWM_CMPVx Address: 0x40000130 [0], 0x40000140 [1], 0x40000150 [2], 0x40000160 [3], 0x40000170 [4], 0x40000180 [5], 0x40000190 [6], 0x400001A0 [7] Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVM 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 16 bits (channel counter size) of field CV are significant.
40.7.37 PWM Comparison x Value Update Register Name: PWM_CMPVUPDx Address: 0x40000134 [0], 0x40000144 [1], 0x40000154 [2], 0x40000164 [3], 0x40000174 [4], 0x40000184 [5], 0x40000194 [6], 0x400001A4 [7] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVMUPD 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
40.7.38 PWM Comparison x Mode Register Name: PWM_CMPMx Address: 0x40000138 [0], 0x40000148 [1], 0x40000158 [2], 0x40000168 [3], 0x40000178 [4], 0x40000188 [5], 0x40000198 [6], 0x400001A8 [7] Access: Read/Write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 21 20 19 18 CUPRCNT 15 14 13 6 12 17 16 11 10 9 8 1 – 0 CEN CPR 5 4 CTR 24 – CUPR CPRCNT 7 25 – 3 – 2 – CEN: Comparison x Enable 0: The comparison x is disabled and can not match. 1: The comparison x is enabled and can match.
40.7.39 PWM Comparison x Mode Update Register Name: PWM_CMPMUPDx Address: 0x4000013C [0], 0x4000014C [1], 0x4000015C [2], 0x4000016C [3], 0x4000017C [4], 0x4000018C [5], 0x4000019C [6], 0x400001AC [7] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 – 11 7 6 5 4 3 – CTRUPD 25 – 24 – 17 16 9 8 1 – 0 CENUPD CUPRUPD 10 CPRUPD 2 – This register acts as a double buffer for the CEN, CTR, CPR and CUPR values.
40.7.40 PWM Channel Mode Register Name: PWM_CMRx [x=0..3] Address: 0x40000200 [0], 0x40000220 [1], 0x40000240 [2], 0x40000260 [3] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 DTLI 17 DTHI 16 DTE 15 – 14 – 13 – 12 – 11 UPDS 10 CES 9 CPOL 8 CALG 7 – 6 – 5 – 4 – 3 2 1 0 CPRE This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center-aligned (flag CHIDx in PWM Interrupt Status Register 1). CALG = 0 (Left Alignment): 0/1: The channel counter event occurs at the end of the PWM period. CALG = 1 (Center Alignment): 0: The channel counter event occurs at the end of the PWM period. 1: The channel counter event occurs at the end of the PWM period and at half the PWM period.
40.7.41 PWM Channel Duty Cycle Register Name: PWM_CDTYx [x=0..3] Address: 0x40000204 [0], 0x40000224 [1], 0x40000244 [2], 0x40000264 [3] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (channel counter size) are significant. CDTY: Channel Duty-Cycle Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
40.7.42 PWM Channel Duty Cycle Update Register Name: PWM_CDTYUPDx [x=0..3] Address: 0x40000208 [0], 0x40000228 [1], 0x40000248 [2], 0x40000268 [3] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle.
40.7.43 PWM Channel Period Register Name: PWM_CPRDx [x=0..3] Address: 0x4000020C [0], 0x4000022C [1], 0x4000024C [2], 0x4000026C [3] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. Only the first 16 bits (channel counter size) are significant.
40.7.44 PWM Channel Period Update Register Name: PWM_CPRDUPDx [x=0..3] Address: 0x40000210 [0], 0x40000230 [1], 0x40000250 [2], 0x40000270 [3] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CPRDUPD 15 14 13 12 CPRDUPD 7 6 5 4 CPRDUPD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the CPRD value.
40.7.45 PWM Channel Counter Register Name: PWM_CCNTx [x=0..3] Address: 0x40000214 [0], 0x40000234 [1], 0x40000254 [2], 0x40000274 [3] Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 16 bits (channel counter size) are significant. CNT: Channel Counter Register Channel counter value.
40.7.46 PWM Channel Dead Time Register Name: PWM_DTx [x=0..3] Address: 0x40000218 [0], 0x40000238 [1], 0x40000258 [2], 0x40000278 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register. Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant.
40.7.47 PWM Channel Dead Time Update Register Name: PWM_DTUPDx [x=0..3] Address: 0x4000021C [0], 0x4000023C [1], 0x4000025C [2], 0x4000027C [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the DTH and DTL values.
40.7.48 PWM Channel Mode Update Register Name: PWM_CMUPDx [x=0..3] Address: 0x40000400 [0], 0x40000420 [1], 0x40000440 [2], 0x40000460 [3] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 CPOLINVUP 12 – 11 – 10 – 9 CPOLUP 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
40.7.49 PWM Channel Additional Edge Register Name: PWM_CAEx [x=0..3] Address: 0x40000404 [0], 0x40000424 [1], 0x40000444 [2], 0x40000464 [3] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 24 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 ADEDGM ADEDGV 15 14 13 12 ADEDGV 7 6 5 4 ADEDGV Only the first 16 bits (channel counter size) are significant. ADEDGV: Channel Additional Edge Value Defines the timing of the additional edge.
40.7.50 PWM Channel Additional Edge Update Register Name: PWM_CAEUPDx [x=0..3] Address: 0x40000408 [0], 0x40000428 [1], 0x40000448 [2], 0x40000468 [3] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 24 ADEDGMUP ADEDGVUP 15 14 13 12 ADEDGVUP 7 6 5 4 ADEDGVUP This register acts as a double buffer for the ADEDGV and ADEDGM values.
41. High Speed MultiMedia Card Interface (HSMCI) 41.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
41.3 Block Diagram Figure 41-1. Block Diagram (4-bit configuration) APB Bridge PDC APB MCCK(1) MCCDA(1) PMC MCK MCDA0(1) HSMCI Interface PIO MCDA1(1) MCDA2(1) MCDA3(1) Interrupt Control HSMCI Interrupt Note: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.
41.4 Application Block Diagram Figure 41-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 10 11 1213 8 SDCard MMC 41.5 Pin Name List Table 41-1. I/O Lines Description for 4-bit Configuration (1) Pin Name Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA3 Data 0..
41.6 Product Dependencies 41.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 41-2. I/O Lines Instance Signal I/O Line Peripheral HSMCI MCCDA PA28 C HSMCI MCCK PA29 C HSMCI MCDA0 PA30 C HSMCI MCDA1 PA31 C HSMCI MCDA2 PA26 C HSMCI MCDA3 PA27 C 41.6.
The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 41-4.
Figure 41-5. SD Memory Card Bus Topology 1 2 3 4 56 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 41-5. Table 41-5.
Command—A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. Response—A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 41-6 and Table 41-7. Table 41-6. ALL_SEND_CID Command Description CMD Index Type Argument Response Abbreviation Command Description CMD2 bcr(1) [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: 1. Table 41-7. bcr means broadcast command with response.
Figure 41-7.
41.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in HSMCI_MR, then all reads and writes use the PDC facilities.
Figure 41-8.
41.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing nonmultiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The flowchart in Figure 41-9 shows how to write a single block with or without use of PDC facilities.
Figure 41-9.
Figure 41-10.
41.9 SD/SDIO Card Operation The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8-bit access only. RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the control/status registers. RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command. CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC devices. 41.10.1 Executing an ATA Polling Command 1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8 KB of DATA. 2.
41.11 HSMCI Boot Operation Mode In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line low after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending on register setting. As it is not possible to boot directly on SD-CARD, a preliminary boot code must be stored in internal Flash. 41.11.1 Boot Procedure, Processor Mode 1. Configure the HSMCI data bus width programming SDCBUS Field in the HSMCI_SDCR.
41.12.3 Write Access During a write access, the XFRDONE flag behaves as shown in Figure 41-12. Figure 41-12. XFRDONE During a Write Access CMD line HSMCI write CMD CMDRDY flag Card response The CMDRDY flag is released 8 tbit after the end of the card response.
41.13 Register Write Protection To prevent any single software error from corrupting HSMCI behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the HSMCI Write Protection Mode Register (HSMCI_WPMR). If a write access to a write-protected register is detected, the WPVS bit in the HSMCI Write Protection Status Register (HSMCI_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
41.14 High Speed MultiMedia Card Interface (HSMCI) User Interface Table 41-8.
41.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0x40080000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN MCIEN: Multi-Media Interface Enable 0: No effect. 1: Enables the Multi-Media Interface if MCDIS is 0. MCIDIS: Multi-Media Interface Disable 0: No effect. 1: Disables the Multi-Media Interface.
41.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0x40080004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 CLKODD 15 PDCMODE 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
PADV: Padding Value 0: 0x00 value is used when padding data in write transfer. 1: 0xFF value is used when padding data in write transfer. PADV may be only in manual transfer. PDCMODE: PDC-oriented Mode 0: Disables PDC transfer 1: Enables PDC transfer. In this case, UNRE and OVRE flags in the HSMCI Status Register (HSMCI_SR) are deactivated after the PDC transfer has been completed.
41.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0x40080008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
41.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0x4008000C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register. SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
41.14.
41.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0x40080014 Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD).
OPDCMD: Open Drain Command 0 (PUSHPULL): Push pull command. 1 (OPENDRAIN): Open drain command. MAXLAT: Max Latency for Command to Response 0 (5): 5-cycle max latency. 1 (64): 64-cycle max latency. TRCMD: Transfer Command Value Name Description 0 NO_DATA 1 START_DAT A Start data transfer 2 STOP_DATA Stop data transfer 3 – No data transfer Reserved TRDIR: Transfer Direction 0 (WRITE): Write. 1 (READ): Read.
DTOMUL and DTOCYC fields located in the HSMCI_DTOR. If the acknowledge pattern is not received then an acknowledge timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set. 41.14.
41.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0x4008001C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
41.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0x40080020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP RSP: Response Note: 1132 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
41.14.
41.14.
41.14.12 HSMCI Status Register Name: HSMCI_SR Address: 0x40080040 Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 – 24 – 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent.
For all the read operations, the NOTBUSY flag is cleared at the end of the host command. For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host command (CMD12). For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block. For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block. The NOTBUSY flag allows to deal with these different states.
RINDE: Response Index Error 0: No error. 1: A mismatch is detected between the command index sent and the response index received. Cleared when writing in the HSMCI_CMDR. RDIRE: Response Direction Error 0: No error. 1: The direction bit from card to host in the response has not been detected. RCRCE: Response CRC Error 0: No error. 1: A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR. RENDE: Response End Bit Error 0: No error.
1: A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR. ACKRCVE: Boot Operation Acknowledge Error 0: No error 1: Corrupted Boot Acknowledge signal received. OVRE: Overrun 0: No error. 1: At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. When FERRCTRL in HSMCI_CFG is set, OVRE becomes reset after read. UNRE: Underrun 0: No error. 1: At least one 8-bit data has been sent without valid information (not written).
41.14.13 HSMCI Interrupt Enable Register Name: HSMCI_IER Address: 0x40080044 Access: Write-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 – 24 – 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
RENDE: Response End Bit Error Interrupt Enable RTOE: Response Time-out Error Interrupt Enable DCRCE: Data CRC Error Interrupt Enable DTOE: Data Time-out Error Interrupt Enable CSTOE: Completion Signal Timeout Error Interrupt Enable FIFOEMPTY: FIFO empty Interrupt enable XFRDONE: Transfer Done Interrupt enable ACKRCV: Boot Acknowledge Interrupt Enable ACKRCVE: Boot Acknowledge Error Interrupt Enable OVRE: Overrun Interrupt Enable UNRE: Underrun Interrupt Enable 114
41.14.14 HSMCI Interrupt Disable Register Name: HSMCI_IDR Address: 0x40080048 Access: Write-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 – 24 – 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
RENDE: Response End Bit Error Interrupt Disable RTOE: Response Time-out Error Interrupt Disable DCRCE: Data CRC Error Interrupt Disable DTOE: Data Time-out Error Interrupt Disable CSTOE: Completion Signal Time out Error Interrupt Disable FIFOEMPTY: FIFO empty Interrupt Disable XFRDONE: Transfer Done Interrupt Disable ACKRCV: Boot Acknowledge Interrupt Disable ACKRCVE: Boot Acknowledge Error Interrupt Disable OVRE: Overrun Interrupt Disable UNRE: Underrun Interrupt
41.14.
RENDE: Response End Bit Error Interrupt Mask RTOE: Response Time-out Error Interrupt Mask DCRCE: Data CRC Error Interrupt Mask DTOE: Data Time-out Error Interrupt Mask CSTOE: Completion Signal Time-out Error Interrupt Mask FIFOEMPTY: FIFO Empty Interrupt Mask XFRDONE: Transfer Done Interrupt Mask ACKRCV: Boot Operation Acknowledge Received Interrupt Mask ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask OVRE: Overrun Interrupt Mask UNRE: Underrun Interrupt M
41.14.16 HSMCI Configuration Register Name: HSMCI_CFG Address: 0x40080054 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
41.14.17 HSMCI Write Protection Mode Register Name: HSMCI_WPMR Address: 0x400800E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protect Enable 0: Disables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII). 1: Enables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII). See Section 41.
41.14.18 HSMCI Write Protection Status Register Name: HSMCI_WPSR Address: 0x400800E8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the HSMCI_WPSR. 1: A write protection violation has occurred since the last read of the HSMCI_WPSR.
42. USB Device Port (UDP) 42.1 Description The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) 2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
Block Diagram Figure 42-1. Block Diagram Atmel Bridge APB to MCU Bus txoen eopn Wrapper MCK USB Device UDPCK Dual Port RAM FIFO User Interface Serial Interface Engine Wrapper 42.3 12 MHz txd rxdm Embedded USB Transceiver DDP DDM rxd SIE rxdp udp_int (interrupt line) Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers.
The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pull-up on DDP must be disabled in order to prevent feeding current to the host.
42.5 Typical Connection Figure 42-2. Board Schematic to Interface Device Peripheral PIO 5V Bus Monitoring 27 K 47 K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 42.5.1 USB Device Transceiver The USB device transceiver is embedded in the product. However, discrete components are required for each of the following actions: to monitor VBUS voltage for line termination to disconnect the host for reduced power consumption 42.5.
42.6 Functional Description 42.6.1 USB 2.0 Full-speed Introduction The USB 2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 42-3. Example of USB 2.0 Full-speed Communication Control USB Host V2.
42.6.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 42-5.
2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 42.6.2 Handling Transactions with USB 2.0 Device Peripheral 42.6.2.1 Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device.
1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx. 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx. 4.
Figure 42-7.
Figure 42-8.
Figure 42-9.
4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx. 7.
42.6.2.4 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) To abort the current request, a protocol stall is used, but uniquely with control transfer.
42.6.2.5 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 42-1 ”USB Endpoint Description”. Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.
42.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 42-14.
42.6.3.2 Entering Attached State To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pull-up connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled. 42.6.3.
42.6.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pull-up shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks.
42.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 42-6.
42.7.1 UDP Frame Number Register Name: UDP_FRM_NUM Address: 0x40084000 Access: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
42.7.2 UDP Global State Register Name: UDP_GLB_STAT Address: 0x40084004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 RMWUPE 3 RSMINPR 2 ESR 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0.
RMWUPE: Remote Wake Up Enable 0: The Remote Wake Up feature of the device is disabled. 1: The Remote Wake Up feature of the device is enabled.
42.7.3 UDP Function Address Register Name: UDP_FADDR Address: 0x40084008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
42.7.
SOFINT: Enable Start Of Frame Interrupt 0: No effect 1: Enables Start Of Frame Interrupt WAKEUP: Enable UDP bus Wakeup Interrupt 0: No effect 1: Enables USB bus Interrupt SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 1171
42.7.
SOFINT: Disable Start Of Frame Interrupt 0: No effect 1: Disables Start Of Frame Interrupt WAKEUP: Disable USB Bus Interrupt 0: No effect 1: Disables USB Bus Wakeup Interrupt SAM4E [DATASHEET] Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14 1173
42.7.
SOFINT: Mask Start Of Frame Interrupt 0: Start of Frame Interrupt is disabled 1: Start of Frame Interrupt is enabled BIT12: UDP_IMR Bit 12 Bit 12 of UDP_IMR cannot be masked and is always read at 1. WAKEUP: USB Bus WAKEUP Interrupt 0: USB Bus Wakeup Interrupt is disabled 1: USB Bus Wakeup Interrupt is enabled Note: When the USB block is in suspend mode, the application may power down the USB logic.
42.7.
RXRSM: UDP Resume Interrupt Status 0: No UDP Resume Interrupt pending 1: UDP Resume Interrupt has been raised The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR. SOFINT: Start of Frame Interrupt Status 0: No Start of Frame Interrupt pending 1: Start of Frame Interrupt has been raised This interrupt is raised each time a SOF token has been detected.
42.7.
42.7.
42.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK) Name: UDP_CSRx [x = 0..
/// Clears the specified bit(s) in the UDP_CSR register. /// \param endpoint The endpoint number of the CSR to process. /// \param flags The bitmap to clear to 0.
RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0: No setup packet available. 1: A setup data packet has been sent by the host and is available in the FIFO. Write: 0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1: No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0: Normal state 1: Stall state Write: 0: Return to normal state 1: Send STALL to the host Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake.
EPTYPE[2:0]: Endpoint Type Read/Write Value Name Description 0 CTRL Control 1 ISO_OUT Isochronous OUT 5 ISO_IN Isochronous IN 2 BULK_OUT Bulk OUT 6 BULK_IN Bulk IN 3 INT_OUT Interrupt OUT 7 INT_IN Interrupt IN DTGLE: Data Toggle Read-only: 0: Identifies DATA0 packet 1: Identifies DATA1 packet Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
42.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS) Name: UDP_CSRx [x = 0..
RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0: No setup packet available. 1: A setup data packet has been sent by the host and is available in the FIFO. Write: 0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1: No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device.
FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0: Normal state. 1: Stall state. Write: 0: Return to normal state. 1: Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
EPTYPE[2:0]: Endpoint Type Read/Write Value Name Description 0 CTRL Control 1 ISO_OUT Isochronous OUT 5 ISO_IN Isochronous IN 2 BULK_OUT Bulk OUT 6 BULK_IN Bulk IN 3 INT_OUT Interrupt OUT 7 INT_IN Interrupt IN DTGLE: Data Toggle Read-only 0: Identifies DATA0 packet 1: Identifies DATA1 packet Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
42.7.12 UDP FIFO Data Register Name: UDP_FDRx [x = 0..7] Address: 0x40084050 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx is the number of bytes to be read from the FIFO (sent by the host).
42.7.13 UDP Transceiver Control Register Name: UDP_TXVC Address: 0x40084074 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 PUON TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.
43. Ethernet MAC (GMAC) 43.1 Description The Ethernet MAC (GMAC) module implements a 10/100 Mbps Ethernet MAC compatible with the IEEE 802.3 standard. The GMAC can operate in either half or full duplex mode at all supported speeds. The Network Configuration Register is used to select the speed, duplex mode and interface type (MII ). The GMAC comprises two constituent components: 43.
43.3 Block Diagram Figure 43-1.
43.4 Signal Interface The GMAC includes the following signal interfaces MII, to an external PHY MDIO interface for external PHY management Slave APB interface for accessing GMAC registers Master AHB interface for memory access Table 43-1. 43.5 GMAC connections in the different modes Signal Name Function MII GTXCK Transmit Clock or Reference Clock TXCK GTXEN Transmit Enable TXEN GTX[3..
43.5.2 1588 Time Stamp Unit The 1588 time stamp unit (TSU) is a timer implemented as a 62-bit timer comprising two registers (GMAC_TSL and GMAC_TN). The 32 upper bits count seconds and are accessible in the “1588 Timer Seconds [31:0] Register” (GMAC_TSL). The 30 lower bits count nanoseconds and are accessible in the “1588 Timer Nanoseconds Register” (GMAC_TN). The 30 lower bits roll over when they have counted to one second.
Table 43-2. Bit 0 Receive Buffer Descriptor Entry (Continued) Function Ownership—needs to be zero for the GMAC to write data to the receive buffer. The GMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again.
Table 43-2. Receive Buffer Descriptor Entry (Continued) Bit Function 20 Priority tag detected—type ID of 0x8100 and null VLAN identifier. For packets incorporating the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of 0x8100 and a null VLAN identifier. 19:17 VLAN priority—only valid if bit 21 is set. 16 Canonical format indicator (CFI) bit (only valid if bit 21 is set). 15 End of frame—when set the buffer contains the end of a frame.
To function properly, a 10/100 Ethernet system should have no excessive length frames or frames greater than 128 bytes with CRC errors. Collision fragments will be less than 128 bytes long, therefore it will be a rare occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 bytes for the receive buffers size.
There is a transmit error such as too many retries or a transmit underrun. To set TXGO, write TSTART to the bit 9 of the Network Control Register. Transmit halt does not take effect until any ongoing transmit finishes. If the DMA is configured for internal FIFO mode, transmission will automatically restart from the first buffer of the frame. If a used bit is read mid way through transmission of a multi buffer frame this is treated as a transmit error.
Table 43-3. Bit Transmit Buffer Descriptor Entry (Continued) Function No CRC to be appended by MAC. When set, this implies that the data in the buffers already contains a valid CRC, hence no CRC or padding is to be appended to the current frame by the MAC. 16 This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a frame.
The back off time is based on an XOR of the 10 least significant bits of the data coming from FIFO and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error will be indicated and no further attempts will be made if 16 consecutive attempts cause collision.
Each discarded frame is counted in the 10 bit length field error statistics register. Frames where the length field is greater than or equal to 0x0600 hex will not be checked. 43.5.6 Checksum Offload for IP, TCP and UDP The GMAC can be programmed to perform IP, TCP and UDP checksum offloading in both receive and transmit directions, which is enabled by setting bit 24 in the Network Configuration Register for receive.
the frame, is the group or individual bit. This is one for multicast addresses and zero for unicast. The all ones address is the broadcast address and a special case of multicast. The GMAC supports recognition of four specific addresses. Each specific address requires two registers, Specific Address Register Bottom and Specific Address Register Top. Specific Address Register Bottom stores the first four bytes of the destination address and Specific Address Register Top contains the last two bytes.
And for a successful match to the type ID, the following Type ID Match 1 Register must be set up: Type ID Match 1 Register (GMAC_TIDM1) (Address 0x0A8) 0x80004321 43.5.8 Broadcast Address Frames with the broadcast address of 0xFFFFFFFFFFFF are stored to memory only if the 'no broadcast' bit in the Network Configuration Register is set to zero. 43.5.9 Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map.
43.5.12 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 43-4. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these extra four bytes, the GMAC can accept frame lengths up to 1536 bytes by setting bit 8 in the Network Configuration Register.
at both ends of a link send both types of frames (regardless of whether they contain a master or slave clock). The Pdelay_Resp message contains the time at which a Pdelay_Req was received and is itself an event message. The time at which a Pdelay_Resp message is received is returned in a Pdelay_Resp_Follow_Up message. 1588 version 2 introduces transparent clocks of which there are two kinds, peer-to-peer (P2P) and end-to-end (E2E).
Table 43-6.
Table 43-8. Example of Pdelay_Req Frame in 1588 Version 2 (UDP/IPv4) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–33) E000006B source IP port (Octets 34–35) — dest IP port (Octets 36–37) 013F other stuff (Octets 38–41) — message type (Octet 42) 02 version PTP (Octet 43) 02 Table 43-9.
Table 43-10.
The timer is implemented as a 62-bit register with the upper 32 bits counting seconds and the lower 30 bits counting nanoseconds. The lower 30 bits roll over when they have counted to one second. An interrupt is generated when the seconds increment. The timer value can be read, written and adjusted through the APB interface. The timer is clocked by MCK. The amount by which the timer increments each clock cycle is controlled by the timer increment register.
interrupt bit 12 of the Interrupt Status Register. Pause frames received with zero quantum are indicated on bit 13 of the Interrupt Status Register. Once the Pause Time Register is loaded and the frame currently being transmitted has been sent, no new frames are transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of transmission, only occurs when the GMAC is configured for full duplex operation.
43.5.16 MAC PFC Priority-based Pause Frame Support Note: Refer to the 802.1Qbb standard for a full description of priority-based pause operation. The following table shows the start of a Priority-based Flow Control (PFC) pause frame. Table 43-14.
Transmitted pause frames comprise the following: A destination address of 01-80-C2-00-00-01 A source address taken from Specific Address Register 1 A type ID of 88-08 (MAC control frame) A pause opcode of 01-01 A priority enable vector taken from Transmit PFC Pause Register 8 pause quantum registers Fill of 00 to take the frame to minimum frame length Valid FCS The pause quantum registers used in the generated frame will depend on the trigger source for the frame as follows:
43.6 Programming Interface 43.6.1 Initialization 43.6.1.1 Configuration Initialization of the GMAC configuration (e.g., loop back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the Network Control Register and Network Configuration Register earlier in this document. To change loop back mode, the following sequence of operations must be followed: 1. Write to Network Control Register to disable transmit and receive circuits. 2.
43.6.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries as defined in Table 43-3, “Transmit Buffer Descriptor Entry”. The Transmit Buffer Queue Pointer Register points to this data structure. To create this list of buffers: 1.
At reset all interrupts are disabled. To enable an interrupt, write to Interrupt Enable Register with the pertinent interrupt bit set to 1. To disable an interrupt, write to Interrupt Disable Register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read Interrupt Mask Register. If the bit is set to 1, the interrupt is disabled. 43.6.1.7 Transmitting Frames To set up a frame for transmission: 1. Enable transmit in the Network Control Register. 2.
Pause Frames Transmitted Register 128 to 255 Byte Frames Received Register 64 Byte Frames Transmitted Register 256 to 511 Byte Frames Received Register 65 to 127 Byte Frames Transmitted Register 512 to 1023 Byte Frames Received Register 128 to 255 Byte Frames Transmitted Register 1024 to 1518 Byte Frames Received Register 256 to 511 Byte Frames Transmitted Register 1519 to Maximum Byte Frames Received Register 512 to 1023 Byte Frames Transmitted Register Undersize Frames Received Register 1024 t
43.7 Ethernet MAC (GMAC) User Interface Table 43-15.
Table 43-15.
Table 43-15.
43.7.1 Network Control Register Name: GMAC_NCR Address: 0x40034000 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 FNP 17 TXPBPF 16 ENPBPR 15 SRTSM 14 – 13 – 12 TXZQPF 11 TXPF 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TXEN 2 RXEN 1 LBL 0 – LBL: Loop Back Local Connects GTX to GRX, GTXEN to GRXDV and forces full duplex mode.
THALT: Transmit Halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends. TXPF: Transmit Pause Frame Writing one to this bit causes a pause frame to be transmitted. TXZQPF: Transmit Zero Quantum Pause Frame Writing one to this bit causes a pause frame with zero quantum to be transmitted. SRTSM: Store Receive Time Stamp to Memory 0: Normal operation.
43.7.2 Network Configuration Register Name: GMAC_NCFGR Address: 0x40034004 Access: Read/Write 31 – 30 IRXER 29 RXBP 28 IPGSEN 27 – 26 IRXFCS 25 EFRHD 24 RXCOEN 23 DCPF 22 21 20 19 CLK 18 17 RFCS 16 LFERD 14 13 PEN 12 RTY 11 – 10 – 9 – 8 MAXFS 6 MTI HEN 5 NBC 4 CAF 3 JFRAME 2 DNVLAN 1 FD 0 SPD DBW 15 RXBUFO 7 UNIHEN SPD: Speed Set to logic one to indicate 100 Mbps operation, logic zero for 10 Mbps.
RTY: Retry Test Must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every GRXCK cycle. PEN: Pause Enable When set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated.
IRXFCS: Ignore RX FCS When set, frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero. IPGSEN: IP Stretch Enable When set, the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG Stretch Register.
43.7.3 Network Status Register Name: GMAC_NSR Address: 0x40034008 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – MDIO: MDIO Input Status Returns status of the MDIO pin. IDLE: PHY Management Logic Idle The PHY management logic is idle (i.e., has completed).
43.7.4 User Register Name: GMAC_UR Address: 0x4003400C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MII MII: MII Mode This bit must be set to 1. Warning: The default value of this bit is 0.
43.7.5 DMA Configuration Register Name: GMAC_DCFGR Address: 0x40034010 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 DRBS 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ESPA 6 ESMA 5 – 4 3 2 FBLDO 1 0 FBLDO: Fixed Burst Length for DMA Data Operations: Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management operations and only used where space and data size allow.
DRBS: DMA Receive Buffer Size DMA receive buffer size in AHB system memory. The value defined by these bits determines the size of buffer to use in main AHB system memory when writing received data. The value is defined in multiples of 64 bytes, thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc.
43.7.6 Transmit Status Register Name: GMAC_TSR Address: 0x40034014 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 HRESP 7 – 6 UND 5 TXCOMP 4 TFC 3 TXGO 2 RLE 1 COL 0 UBR UBR: Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Writing a one clears this bit. COL: Collision Occurred Set by the assertion of collision. Writing a one clears this bit.
HRESP: HRESP Not OK Set when the DMA block sees HRESP not OK. Writing a one clears this bit.
43.7.7 Receive Buffer Queue Base Address Register Name: GMAC_RBQB Address: 0x40034018 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the Network Control Register.
43.7.8 Transmit Buffer Queue Base Address Register Name: GMAC_TBQB Address: 0x4003401C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register.
43.7.9 Receive Status Register Name: GMAC_RSR Address: 0x40034020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 HNO 2 RXOVR 1 REC 0 BNA This register, when read, provides receive status details. Once read, individual bits may be cleared by writing a one to them. It is not possible to set a bit to 1 by writing to the register.
43.7.10 Interrupt Status Register Name: GMAC_ISR Address: 0x40034024 Access: Read-only 31 – 30 – 29 – 28 WOL 27 – 26 SRI 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 – 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS This register indicates the source of the interrupt.
ROVR: Receive Overrun Set when the receive overrun status bit is set. Cleared on read. HRESP: HRESP Not OK Set when the DMA block sees HRESP not OK. Cleared on read. PFNZ: Pause Frame with Non-zero Pause Quantum Received Indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read. PTZ: Pause Time Zero Set when either the Pause Time Register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field.
43.7.11 Interrupt Enable Register Name: GMAC_IER Address: 0x40034028 Access: Write-only 31 – 30 – 29 – 28 WOL 27 – 26 SRI 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 EXINT 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt.
PFNZ: Pause Frame with Non-zero Pause Quantum Received Enable pause frame with non-zero pause quantum interrupt. PTZ: Pause Time Zero Enable pause time zero interrupt. PFTR: Pause Frame Transmitted Enable pause frame transmitted interrupt. EXINT: External Interrupt Enable external interrupt. DRQFR: PTP Delay Request Frame Received Enable PTP delay_req frame received. SFR: PTP Sync Frame Received Enable PTP sync frame received.
43.7.12 Interrupt Disable Register Name: GMAC_IDR Address: 0x4003402C Access: Write-only 31 – 30 – 29 – 28 WOL 27 – 26 SRI 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 EXINT 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS Writing a one to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
PFNZ: Pause Frame with Non-zero Pause Quantum Received Disable pause frame with non-zero pause quantum interrupt. PTZ: Pause Time Zero Disable pause time zero interrupt. PFTR: Pause Frame Transmitted Disable pause frame transmitted interrupt. EXINT: External Interrupt Disable external interrupt. DRQFR: PTP Delay Request Frame Received Disable PTP delay_req frame received. SFR: PTP Sync Frame Received Disable PTP sync frame received.
43.7.13 Interrupt Mask Register Name: GMAC_IMR Address: 0x40034030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 EXINT 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS The Interrupt Mask Register is a read-only register indicating which interrupts are masked.
TXUBR: TX Used Bit Read A read of this register returns the value of the transmit used bit read interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written. TUR: Transmit Underrun A read of this register returns the value of the transmit buffer underrun interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled.
HRESP: HRESP Not OK A read of this register returns the value of the HRESP not OK interrupt mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written. PFNZ: Pause Frame with Non-zero Pause Quantum Received A read of this register returns the value of the pause frame with non-zero pause quantum interrupt mask. 0: Interrupt is enabled.
SFR: PTP Sync Frame Received A read of this register returns the value of the PTP sync frame received mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written. DRQFT: PTP Delay Request Frame Transmitted A read of this register returns the value of the PTP delay_req frame transmitted mask. 0: Interrupt is enabled.
PDRSFT: PDelay Response Frame Transmitted A read of this register returns the value of the PTP pdelay_resp frame transmitted mask. 0: Interrupt is enabled. 1: Interrupt is disabled. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written.
43.7.14 PHY Maintenance Register Name: GMAC_MAN Address: 0x40034034 Access: Read/Write 31 WZO 30 CLTTO 29 23 PHYA 22 21 15 14 28 27 26 OP 13 25 24 17 16 PHYA 20 REGA 19 18 WTN 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA The PHY Maintenance Register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit 2 is set in the Network Status Register.
WZO: Write ZERO Must be written with 0.
43.7.15 Receive Pause Quantum Register Name: GMAC_RPQ Address: 0x40034038 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RPQ 7 6 5 4 RPQ RPQ: Received Pause Quantum Stores the current value of the Receive Pause Quantum Register which is decremented every 512 bit times.
43.7.16 Transmit Pause Quantum Register Name: GMAC_TPQ Address: 0x4003403C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TPQ 7 6 5 4 TPQ TPQ: Transmit Pause Quantum Written with the pause quantum value for pause frame transmission.
43.7.17 Hash Register Bottom [31:0] Name: GMAC_HRB Address: 0x40034080 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The unicast hash enable (UNIHEN) and the multicast hash enable (MITIHEN) bits in the Network Configuration Register (Section 43.7.2 “Network Configuration Register”) enable the reception of hash matched frames. See Section 43.5.9 “Hash Addressing”.
43.7.18 Hash Register Top [63:32] Name: GMAC_HRT Address: 0x40034084 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The unicast hash enable (UNIHEN) and the multicast hash enable (MITIHEN) bits in the Network Configuration Register enable the reception of hash matched frames. See Section 43.5.9 “Hash Addressing”. ADDR: Hash Address Bits 63 to 32 of the Hash Address Register.
43.7.19 Specific Address 1 Bottom [31:0] Register Name: GMAC_SAB1 Address: 0x40034088 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.20 Specific Address 1 Top [47:32] Register Name: GMAC_SAT1 Address: 0x4003408C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.21 Specific Address 2 Bottom [31:0] Register Name: GMAC_SAB2 Address: 0x40034090 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.22 Specific Address 2 Top [47:32] Register Name: GMAC_SAT2 Address: 0x40034094 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.23 Specific Address 3 Bottom [31:0] Register Name: GMAC_SAB3 Address: 0x40034098 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.24 Specific Address 3 Top [47:32] Register Name: GMAC_SAT3 Address: 0x4003409C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.25 Specific Address 4 Bottom Register[31:0] Name: GMAC_SAB4 Address: 0x400340A0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.26 Specific Address 4 Top Register[47:32] Name: GMAC_SAT4 Address: 0x400340A4 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
43.7.27 Type ID Match 1 Register Name: GMAC_TIDM1 Access: Read/Write 31 ENID1 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 1 When enabled, TID is compared against the length/type ID of the frame being received (e.g. bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and the frame is copied to memory if a match is found.
43.7.28 Type ID Match 2 Register Name: GMAC_TIDM2 Access: Read/Write 31 ENID2 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 2 When enabled, TID is compared against the length/type ID of the frame being received (e.g. bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and the frame is copied to memory if a match is found.
43.7.29 Type ID Match 3 Register Name: GMAC_TIDM3 Access: Read/Write 31 ENID3 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 3 When enabled, TID is compared against the length/type ID of the frame being received (e.g. bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and the frame is copied to memory if a match is found.
43.7.30 Type ID Match 4 Register Name: GMAC_TIDM4 Access: Read/Write 31 ENID4 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 4 When enabled, TID is compared against the length/type ID of the frame being received (e.g. bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and the frame is copied to memory if a match is found.
43.7.31 IPG Stretch Register Name: GMAC_IPGS Address: 0x400340BC Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 FL 7 6 5 4 FL FL: Frame Length Bits 7:0 are multiplied with the previously transmitted frame length (including preamble). Bits 15:8 +1 divide the frame length.
43.7.32 Stacked VLAN Register Name: GMAC_SVLAN Address: 0x400340C0 Access: Read/Write 31 ESVLAN 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 VLAN_TYPE 7 6 5 4 VLAN_TYPE VLAN_TYPE: User Defined VLAN_TYPE Field User defined VLAN_TYPE field.
43.7.33 Transmit PFC Pause Register Name: GMAC_TPFCP Address: 0x400340C4 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PQ 7 6 5 4 PEV PEV: Priority Enable Vector If bit 17 of the Network Control Register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0].
43.7.34 Specific Address 1 Mask Bottom [31:0] Register Name: GMAC_SAMB1 Address: 0x400340C8 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR: Specific Address 1 Mask Setting a bit to one masks the corresponding bit in the Specific Address 1 Register.
43.7.35 Specific Address Mask 1 Top [47:32] Register Name: GMAC_SAMT1 Address: 0x400340CC Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR ADDR: Specific Address 1 Mask Setting a bit to one masks the corresponding bit in the Specific Address 1 Register.
43.7.36 Octets Transmitted [31:0] Register Name: GMAC_OTLO Address: 0x40034100 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXO 23 22 21 20 TXO 15 14 13 12 TXO 7 6 5 4 TXO When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. TXO: Transmitted Octets Transmitted octets in frame without errors [31:0].
43.7.37 Octets Transmitted [47:32] Register Name: GMAC_OTHI Address: 0x40034104 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXO 7 6 5 4 TXO When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. TXO: Transmitted Octets Transmitted octets in frame without errors [47:32].
43.7.38 Frames Transmitted Register Name: GMAC_FT Address: 0x40034108 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FTX 23 22 21 20 FTX 15 14 13 12 FTX 7 6 5 4 FTX FTX: Frames Transmitted without Error Frames transmitted without error. This register counts the number of frames successfully transmitted, i.e., no underrun and not too many retries. Excludes pause frames.
43.7.39 Broadcast Frames Transmitted Register Name: GMAC_BCFT Address: 0x4003410C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BFTX 23 22 21 20 BFTX 15 14 13 12 BFTX 7 6 5 4 BFTX BFTX: Broadcast Frames Transmitted without Error Broadcast frames transmitted without error. This register counts the number of broadcast frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames.
43.7.40 Multicast Frames Transmitted Register Name: GMAC_MFT Address: 0x40034110 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MFTX 23 22 21 20 MFTX 15 14 13 12 MFTX 7 6 5 4 MFTX MFTX: Multicast Frames Transmitted without Error This register counts the number of multicast frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames.
43.7.41 Pause Frames Transmitted Register Name: GMAC_PFT Address: 0x40034114 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 15 22 – 14 21 – 13 20 – 12 19 – 11 18 – 10 17 – 9 16 – 8 3 2 1 0 PFTX 7 6 5 4 PFTX PFTX: Pause Frames Transmitted Register This register counts the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames.
43.7.42 64 Byte Frames Transmitted Register Name: GMAC_BFT64 Address: 0x40034118 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 64 Byte Frames Transmitted without Error This register counts the number of 64 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames.
43.7.43 65 to 127 Byte Frames Transmitted Register Name: GMAC_TBFT127 Address: 0x4003411C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 65 to 127 Byte Frames Transmitted without Error This register counts the number of 65 to 127 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames.
43.7.44 128 to 255 Byte Frames Transmitted Register Name: GMAC_TBFT255 Address: 0x40034120 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 128 to 255 Byte Frames Transmitted without Error This register counts the number of 128 to 255 byte frames successfully transmitted without error, i.e., no underrun and not too many retries.
43.7.45 256 to 511 Byte Frames Transmitted Register Name: GMAC_TBFT511 Address: 0x40034124 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 256 to 511 Byte Frames Transmitted without Error This register counts the number of 256 to 511 byte frames successfully transmitted without error, i.e., no underrun and not too many retries.
43.7.46 512 to 1023 Byte Frames Transmitted Register Name: GMAC_TBFT1023 Address: 0x40034128 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 512 to 1023 Byte Frames Transmitted without Error This register counts the number of 512 to 1023 byte frames successfully transmitted without error, i.e., no underrun and not too many retries.
43.7.47 1024 to 1518 Byte Frames Transmitted Register Name: GMAC_TBFT1518 Address: 0x4003412C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 1024 to 1518 Byte Frames Transmitted without Error This register counts the number of 1024 to 1518 byte frames successfully transmitted without error, i.e., no underrun and not too many retries.
43.7.48 Greater Than 1518 Byte Frames Transmitted Register Name: GMAC_GTBFT1518 Address: 0x40034130 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: Greater than 1518 Byte Frames Transmitted without Error This register counts the number of 1518 or above byte frames successfully transmitted without error i.e., no underrun and not too many retries.
43.7.49 Transmit Underruns Register Name: GMAC_TUR Address: 0x40034134 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 TXUNR 0 TXUNR TXUNR: Transmit Underruns This register counts the number of frames not transmitted due to a transmit underrun. If this register is incremented then no other statistics register is incremented.
43.7.50 Single Collision Frames Register Name: GMAC_SCF Address: 0x40034138 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 16 15 14 13 12 11 10 9 8 3 2 1 0 SCOL SCOL 7 6 5 4 SCOL SCOL: Single Collision This register counts the number of frames experiencing a single collision before being successfully transmitted i.e., no underrun.
43.7.51 Multiple Collision Frames Register Name: GMAC_MCF Address: 0x4003413C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 16 15 14 13 12 11 10 9 8 3 2 1 0 MCOL MCOL 7 6 5 4 MCOL MCOL: Multiple Collision This register counts the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
43.7.52 Excessive Collisions Register Name: GMAC_EC Address: 0x40034140 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 XCOL XCOL XCOL: Excessive Collisions This register counts the number of frames that failed to be transmitted because they experienced 16 collisions.
43.7.53 Late Collisions Register Name: GMAC_LC Address: 0x40034144 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 LCOL 0 LCOL LCOL: Late Collisions This register counts the number of late collisions occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e., both as a collision and a late collision.
43.7.54 Deferred Transmission Frames Register Name: GMAC_DTF Address: 0x40034148 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 16 15 14 13 12 11 10 9 8 3 2 1 0 DEFT DEFT 7 6 5 4 DEFT DEFT: Deferred Transmission This register counts the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission.
43.7.
43.7.56 Octets Received [31:0] Register Name: GMAC_ORLO Address: 0x40034150 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXO 23 22 21 20 RXO 15 14 13 12 RXO 7 6 5 4 RXO When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation. RXO: Received Octets Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type.
43.7.57 Octets Received [47:32] Register Name: GMAC_ORHI Address: 0x40034154 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXO 7 6 5 4 RXO When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. RXO: Received Octets Received octets in frame without errors [47:32].
43.7.58 Frames Received Register Name: GMAC_FR Address: 0x40034158 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRX 23 22 21 20 FRX 15 14 13 12 FRX 7 6 5 4 FRX FRX: Frames Received without Error Frames received without error. This register counts the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
43.7.59 Broadcast Frames Received Register Name: GMAC_BCFR Address: 0x4003415C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BFRX 23 22 21 20 BFRX 15 14 13 12 BFRX 7 6 5 4 BFRX BFRX: Broadcast Frames Received without Error Broadcast frames received without error. This register counts the number of broadcast frames successfully received.
43.7.60 Multicast Frames Received Register Name: GMAC_MFR Address: 0x40034160 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MFRX 23 22 21 20 MFRX 15 14 13 12 MFRX 7 6 5 4 MFRX MFRX: Multicast Frames Received without Error This register counts the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
43.7.61 Pause Frames Received Register Name: GMAC_PFR Address: 0x40034164 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PFRX 7 6 5 4 PFRX PFRX: Pause Frames Received Register This register counts the number of pause frames received without error.
43.7.62 64 Byte Frames Received Register Name: GMAC_BFR64 Address: 0x40034168 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 64 Byte Frames Received without Error This register counts the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
43.7.63 65 to 127 Byte Frames Received Register Name: GMAC_TBFR127 Address: 0x4003416C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 65 to 127 Byte Frames Received without Error This register counts the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
43.7.64 128 to 255 Byte Frames Received Register Name: GMAC_TBFR255 Address: 0x40034170 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 128 to 255 Byte Frames Received without Error This register counts the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
43.7.65 256 to 511 Byte Frames Received Register Name: GMAC_TBFR511 Address: 0x40034174 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 256 to 511 Byte Frames Received without Error This register counts the number of 256 to 511 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
43.7.66 512 to 1023 Byte Frames Received Register Name: GMAC_TBFR1023 Address: 0x40034178 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 512 to 1023 Byte Frames Received without Error This register counts the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
43.7.67 1024 to 1518 Byte Frames Received Register Name: GMAC_TBFR1518 Address: 0x4003417C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 1024 to 1518 Byte Frames Received without Error This register counts the number of 1024 to 1518 byte frames successfully received without error, i.e., no underrun and not too many retries.
43.7.68 1519 to Maximum Byte Frames Received Register Name: GMAC_TMXBFR Address: 0x40034180 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 1519 to Maximum Byte Frames Received without Error This register counts the number of 1519 byte or above frames successfully received without error.
43.7.69 Undersized Frames Received Register Name: GMAC_UFR Address: 0x40034184 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 UFRX 0 UFRX UFRX: Undersize Frames Received This register counts the number of frames received less than 64 bytes in length (10/100 mode, full duplex) that do not have either a CRC error or an alignment error.
43.7.
43.7.71 Jabbers Received Register Name: GMAC_JR Address: 0x4003418C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 JRX 0 JRX JRX: Jabbers Received The register counts the number of frames received exceeding 1518 bytes in length (1536 if bit 8 is set in Network Configuration Register) and have either a CRC error, an alignment error or a receive symbol error.
43.7.72 Frame Check Sequence Errors Register Name: GMAC_FCSE Address: 0x40034190 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 FCKR 0 FCKR FCKR: Frame Check Sequence Errors The register counts frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 is set in Network Configuration Register).
43.7.73 Length Field Frame Errors Register Name: GMAC_LFFE Address: 0x40034194 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 LFER 0 LFER LFER: Length Field Frame Errors This register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14).
43.7.74 Receive Symbol Errors Register Name: GMAC_RSE Address: 0x40034198 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 RXSE 0 RXSE RXSE: Receive Symbol Errors This register counts the number of frames that had GRXER asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks.
43.7.
43.7.
43.7.77 Receive Overruns Register Name: GMAC_ROE Address: 0x400341A4 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 RXOVR 0 RXOVR RXOVR: Receive Overruns This register counts the number of frames that are address recognized but were not copied to memory due to a receive overrun.
43.7.
43.7.
43.7.
43.7.81 1588 Timer Sync Strobe Seconds [31:0] Register Name: GMAC_TSSSL Address: 0x400341C8 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VTS 23 22 21 20 VTS 15 14 13 12 VTS 7 6 5 4 VTS VTS: Value of Timer Seconds Register Capture The value of the Timer Seconds Register is captured.
43.7.82 1588 Timer Sync Strobe Nanoseconds Register Name: GMAC_TSSN Address: 0x400341CC Access: Read/Write 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VTN 20 VTN 15 14 13 12 VTN 7 6 5 4 VTN VTN: Value Timer Nanoseconds Register Capture The value of the Timer Nanoseconds Register is captured.
43.7.83 1588 Timer Seconds [31:0] Register Name: GMAC_TSL Address: 0x400341D0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TCS 23 22 21 20 TCS 15 14 13 12 TCS 7 6 5 4 TCS TCS: Timer Count in Seconds This register is writable. It increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented when the Timer Adjust Register is written.
43.7.84 1588 Timer Nanoseconds Register Name: GMAC_TN Address: 0x400341D4 Access: Read/Write 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TNS 20 TNS 15 14 13 12 TNS 7 6 5 4 TNS TNS: Timer Count in Nanoseconds This register is writable. It can also be adjusted by writes to the 1588 Timer Adjust Register. It increments by the value of the 1588 Timer Increment Register each clock cycle.
43.7.85 1588 Timer Adjust Register Name: GMAC_TA Address: 0x400341D8 Access: Write-only 31 ADJ 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ITDT 20 ITDT 15 14 13 12 ITDT 7 6 5 4 ITDT ITDT: Increment/Decrement The number of nanoseconds to increment or decrement the 1588 Timer Nanoseconds Register. If necessary, the 1588 Seconds Register will be incremented or decremented. ADJ: Adjust 1588 Timer Write as one to subtract from the 1588 timer.
43.7.86 1588 Timer Increment Register Name: GMAC_TI Address: 0x400341DC Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 NIT 15 14 13 12 ACNS 7 6 5 4 CNS CNS: Count Nanoseconds A count of nanoseconds by which the 1588 Timer Nanoseconds Register will be incremented each clock cycle.
43.7.87 PTP Event Frame Transmitted Seconds Register Name: GMAC_EFTS Address: 0x400341E0 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.
43.7.88 PTP Event Frame Transmitted Nanoseconds Register Name: GMAC_EFTN Address: 0x400341E4 Access: Read-only 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.
43.7.89 PTP Event Frame Received Seconds Register Name: GMAC_EFRS Address: 0x400341E8 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP receive primary event crosses the MII interface. An interrupt is issued when the register is updated.
43.7.90 PTP Event Frame Received Nanoseconds Register Name: GMAC_EFRN Address: 0x400341EC Access: Read-only 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP receive primary event crosses the MII interface. An interrupt is issued when the register is updated.
43.7.91 PTP Peer Event Frame Transmitted Seconds Register Name: GMAC_PEFTS Address: 0x400341F0 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.
43.7.92 PTP Peer Event Frame Transmitted Nanoseconds Register Name: GMAC_PEFTN Address: 0x400341F4 Access: Read-only 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.
43.7.93 PTP Peer Event Frame Received Seconds Register Name: GMAC_PEFRS Address: 0x400341F8 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP receive primary event crosses the MII interface. An interrupt is issued when the register is updated.
44. 44.1 Analog Comparator Controller (ACC) Description The Analog Comparator Controller (ACC) configures the analog comparator and generates an interrupt depending on user settings. The analog comparator embeds two 8-to-1 multiplexers that generate two internal inputs. These inputs are compared, resulting in a compare output. The hysteresis level, edge detection and polarity are configurable. The ACC also generates a compare event which can be used by the Pulse Width Modulator (PWM).
44.3 Block Diagram Figure 44-1. Analog Comparator Controller Block Diagram Regulator PWM PMC Analog Comparator MCK AND FE 1) bias External Analog Data Inputs inp Mux + SCO MCK Synchro + Edge Detect AND inn - on AND on TS ADVREF DAC0 MCK DAC1 on Mux External 1) Analog Data Inputs Change Detect +Mask Timer on SELPLUS SELMINUS ACEN ISEL HYST SELFS INV MASK CE EDGETYP SCO User Interface CE Interrupt Controller Note 1: Refer to Table 44-1 for the list of analog inputs.
44.4 Pin Name List Table 44-2. ACC Pin List Pin Name Description Type External analog data inputs Input TS On-chip temperature sensor Input ADVREF ADC voltage reference Input DAC0, DAC1 On-chip DAC inputs Input FAULT Drives internal fault input of PWM Output AFE0..AD[5:0] AFE1..AD[1:0] 44.5 Product Dependencies 44.5.1 I/O Lines The analog input pins (AD0-AD7 and DAC0-1) are multiplexed with digital functions (PIO) on the IO line.
44.6 Functional Description 44.6.1 Description The Analog Comparator Controller (ACC) controls the analog comparator settings and performs post-processing of the analog comparator output. When the analog comparator settings are modified, the output of the analog cell may be invalid. The ACC masks the output for the invalid period. A comparison flag is triggered by an event on the output of the analog comparator and an interrupt is generated.
44.7 Analog Comparator Controller (ACC) User Interface Table 44-4.
44.7.1 ACC Control Register Name: ACC_CR Address: 0x400BC000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST SWRST: Software Reset 0: No effect. 1: Resets the module.
44.7.2 ACC Mode Register Name: ACC_MR Address: 0x400BC004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 FE 13 SELFS 12 INV 11 – 10 9 8 ACEN 7 – 6 5 SELPLUS 4 3 – 2 1 SELMINUS 0 EDGETYP This register can only be written if the WPEN bit is cleared in the ACC Write Protection Mode Register. SELMINUS: Selection for Minus Comparator Input 0..
SELPLUS: Selection For Plus Comparator Input 0..7: Selects the input to apply on analog comparator SELPLUS comparison input. Value Name Description 0 AD0 Select AD0 1 AD1 Select AD1 2 AD2 Select AD2 3 AD3 Select AD3 4 AD4 Select AD4 5 AD5 Select AD5 6 AD6 Select AD6 7 AD7 Select AD7 ACEN: Analog Comparator Enable 0 (DIS): Analog comparator disabled. 1 (EN): Analog comparator enabled.
44.7.3 ACC Interrupt Enable Register Name: ACC_IER Address: 0x400BC024 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CE CE: Comparison Edge 0: No effect. 1: Enables the interrupt when the selected edge (defined by EDGETYP) occurs.
44.7.4 ACC Interrupt Disable Register Name: ACC_IDR Address: 0x400BC028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CE CE: Comparison Edge 0: No effect. 1: Disables the interrupt when the selected edge (defined by EDGETYP) occurs.
44.7.5 ACC Interrupt Mask Register Name: ACC_IMR Address: 0x400BC02C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CE CE: Comparison Edge 0: The interrupt is disabled. 1: The interrupt is enabled.
44.7.6 ACC Interrupt Status Register Name: ACC_ISR Address: 0x400BC030 Access: Read-only 31 MASK 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 SCO 0 CE CE: Comparison Edge 0: No edge occurred (defined by EDGETYP) on analog comparator output since the last read of ACC_ISR.
44.7.7 ACC Analog Control Register Name: ACC_ACR Address: 0x400BC094 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 0 ISEL HYST This register can only be written if the WPEN bit is cleared in ACC Write Protection Mode Register. ISEL: Current Selection Refer to the section on ACC electrical characteristics in the datasheet. 0 (LOPW): Low-power option.
44.7.8 ACC Write Protection Mode Register Name: ACC_WPMR Address: 0x400BC0E4 Access: Read/Write Reset: See Table 44-4 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x414343 (“ACC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x414343 (“ACC” in ASCII).
44.7.9 ACC Write Protection Status Register Name: ACC_WPSR Address: 0x400BC0E8 Access: Read-only Reset: See Table 44-4 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WPVS WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of ACC_WPSR.
45. Analog-Front-End Controller (AFEC) 45.1 Description The Analog-Front-End Controller (AFEC) is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an AFE Controller. Refer to the Block Diagram: Figure 45-1. It also integrates a 16-to-1 analog multiplexer, making possible the analog-to-digital conversions of 16 analog lines. The conversions extend from 0V to ADVREF.
45.3 Automatic Window Comparison of Converted Values Register Write Protection Block Diagram Figure 45-1. Analog-Front-End Converter Block Diagram Timer Counter Channels PMC MCK AFE Controller (AFEC) AFEC Interrupt Trigger Selection AFE_ADTRG Interrupt Controller Channel Sequencer VDDANA AFE Analog Cell ADVREF CHENx System Bus AFE_AD0 RES PDC AFE_AD1 Sample and Hold Analog Inputs Multiplexed with I/O lines Analog Mux n->1 S&H Prog.
45.5 Product Dependencies 45.5.1 Power Management The AFE Controller is not continuously clocked. The programmer must first enable the AFE Controller MCK in the Power Management Controller (PMC) before using the AFE Controller. However, if the application does not require AFEC operations, the AFEC clock can be stopped when not needed and restarted when necessary. Configuring the AFE Controller does not require the AFEC clock to be enabled. 45.5.
Table 45-3. I/O Lines AFEC0 AFE0_AD10 PC30 X1 AFEC0 AFE0_AD11 PC31 X1 AFEC0 AFE0_AD12 PC26 X1 AFEC0 AFE0_AD13 PC27 X1 AFEC0 AFE0_AD14 PC0 X1 AFEC1 AFE1_AD0/WKUP12 PB2 X1 AFEC1 AFE1_AD1 PB3 X1 AFEC1 AFE1_AD2 PA21 X1 AFEC1 AFE1_AD3 PA22 X1 AFEC1 AFE1_AD4 PC1 X1 AFEC1 AFE1_AD5 PC2 X1 AFEC1 AFE1_AD6 PC3 X1 AFEC1 AFE1_AD7 PC4 X1 45.5.6 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements.
Figure 45-2. Sequence of AFEC conversions when Tracking time > Conversion time AFECClock Trigger event (Hard or Soft) AFEC_ON Commands from controller to analog cell AFEC_Start CH0 AFEC_SEL CH1 CH2 LCDR CH0 CH1 DRDY Start Up Transfer Period Time (and tracking of CH0) Conversion of CH0 Transfer Period Conversion of CH1 Tracking of CH1 Figure 45-3.
45.6.3 Conversion Resolution The AFEC supports 10-bit or 12-bit native resolutions. The 10-bit selection is performed by writing one to the RES field in the AFEC Extended Mode Register. By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By writing one to the RES field, the AFEC switches to the lowest resolution and the conversion results can be read in the lowest significant bits of the data register.
Figure 45-4. EOCx and DRDY Flag Behavior Write the AFEC_CR with START = 1 Write the AFEC_CR Read the AFEC_CDR with ADC_CSELR.CSEL = x with START = 1 Read the AFEC_LCDR CHx (AFEC_CHSR) EOCx (AFEC_ISR) DRDY (AFEC_ISR) If the AFEC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is set in the Overrun Status Register (AFEC_OVER). Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in AFEC_ISR.
Figure 45-5.
45.6.5 Conversion Results Format The conversion results can be signed (2’s complement) or unsigned depending on the value of the SIGNMODE field of the AFEC_EMR (see Section 45.7.3 “AFEC Extended Mode Register”). Four modes are available: Results of channels configured in single-ended mode are unsigned, results of channels configured in differential mode are signed. Results of channels configured in single-ended mode are signed, results of channels configured in differential mode are unsigned.
This mode can be used when the minimum period of time between two successive trigger events is greater than the startup period of Analog-Digital converter (see the AFEC electrical characteristics in the product datasheet). When a start conversion request occurs, the AFEC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the AFEC is deactivated until the next trigger.
Table 45-4. Input Pins and Channel Number in Single Ended Mode Input Pins Channel Number AFE_AD0 CH0 AFE_AD1 CH1 ... ... AFE_AD14 CH14 AFE_AD15 CH15 Table 45-5. Input Pins and Channel Number In Differential Mode Input Pins Channel Number AFE_AD0-AFE_AD1 CH0 ... ... AFE_AD14-AFE_AD15 CH14 45.6.10 Input Gain and Offset The AFEC has a built in Programmable Gain Amplifier (PGA) and Programmable Offset per channel (through a DAC).
Figure 45-7. Analog Full Scale Ranges in Single Ended/Differential Applications Versus Gain single ended se0fd1 = 0 fully differential se0fd1 = 1 VADVREF VIN+ VIN+ same as gain=1 gain=0.
Warning: No input buffer amplifier to isolate the source is included in the AFEC. This must be taken into consideration to program a precise value in the TRACKTIM field. See the AFEC electrical characteristics of the product datasheet. 45.6.12 Temperature Sensor The temperature sensor is internally connected to channel 15. The measure of the temperature can be made in different ways through the AFE Controller.
Figure 45-8. Non-Optimized Temperature Conversion AFEC_CHSR[TEMP] = 1, AFEC_MR.TRGEN = 1 and AFEC_TEMPMR.RTCT = 0 Internal/External Trigger event C T AFEC_SEL AFEC_CDR[0] C0 AFEC_LCDR T1 T0 C0 T1 C T C T C2 C1 T0 AFEC_CDR[TEMP] C T C1 T2 T3 C2 C5 C4 C3 T2 C T T3 T5 T4 C3 T4 C4 T5 C: Classic AFEC Conversion Sequence - T: Temperature Sensor Channel Assuming AFEC_CHSR[0] = 1 and AFEC_CHSR[TEMP] = 1 where TEMP is the index of the temperature sensor channel trig.
Figure 45-9. Optimized Temperature Conversion combined with classical conversions AFEC_CHSR[TEMP] = 0, AFEC_MR.TRGEN = 1 and AFEC_TEMPMR.RTCT = 1 1s Internal RTC Trigger event Internal/External Trigger event C T AFEC_SEL AFEC_CDR[0] & AFEC_LCDR C0 AFEC_CDR[TEMP] T0 C C T C C1 C2 C3 C C4 T1 C5 T2 C: Classic AFE Conversion Sequence - T: Temperature Sensor Channel Assuming AFEC_CHSR[0] = 1 and A_CHSR[TEMP] = 1 where TEMP is the index of the temperature sensor channel trig.
programmed into the AFEC_TEMPMR by means of TEMPCMPMOD field. These values define the way the TEMPCHG flag will be raised in the AFEC_IS1R. The TEMPCHG flag can be used to trigger an interrupt if there is something to update/modify in the system resulting from a temperature change. In any case, if temperature sensor measure is configured, the temperature can be read at anytime in AFEC_CDR (AFEC_CSELR must be programmed accordingly prior to read AFEC_CDR) without any specific software intervention. 45.6.
Figure 45-11. Digital Averaging Function Waveforms over multiple trigger events AFEC_EMR.RES = 2, STM = 0, AFEC_CHSR[1:0] = 0x3 and AFEC_MR.USEQ = 0 Internal/External Trigger event AFEC_SEL Internal register CDR[0] 0 1 CH0_0 0 1 0i1 0 1 0i2 0 1 0i3 0 1 CH0_1 0i1 Read AFEC_CDR & AFEC_CSELR.CSEL = 0 EOC[0] OVR[0] Internal register CDR[1] CH1_0 1i1 1i2 1i3 CH1_1 Read AFEC_CDR & AFEC_CSELR.
Figure 45-12. Digital Averaging Function Waveforms on a single trigger event AFEC_EMR.RES = 2, STM = 1, AFEC_CHSR[1:0] = 0x3 and AFEC_MR.USEQ = 0 Internal/External Trigger event 0 AFEC_SEL internal register CDR[0] CH0_0 1 0 1 0 1 0i1 0i2 0 0 1 0i3 1 0 1 CH0_1 Read AFEC_CDR & AFEC_CSELR.CSEL = 0 EOC[0] internal register CDR[1] CH1_0 1i1 1i2 1i3 CH1_1 Read AFEC_CDR & AFEC_CSELR.
Figure 45-13. Digital Averaging Function Waveforms on single trigger event, non-interleaved AFEC_EMR.EMR = 2, STM = 1, AFEC_CHSR[7:0] = 0xFF and AFEC_MR.USEQ = 1 AFEC_SEQ1R = 0x1111_0000 Internal/External Trigger event 0 AFEC_SEL internal register CDR[0] 0 0 0 1 CH0_0 0i1 0i2 0i3 0 1 1 1 0 0 0 CH0_1 Read AFEC_CDR & AFEC_CSELR.CSEL = 0 EOC[0] internal register CDR[1] CH1_0 1i1 1i2 1i3 CH1_1 Read AFEC_CDR & AFEC_CSELR.
If a software reset is performed (SWRST bit in AFEC_CR) or after power up (or wake-up from Backup mode), the calibration data in the AFEC memory is lost. Changing the AFEC running mode (in the AFEC_CR) does not affect the calibration data. Changing the AFEC reference voltage (ADVREF pin) requires a new calibration sequence. For calibration time, offset and gain error after calibration, refer to the 12-bit AFEC electrical characteristics of the product datasheet. 45.6.
45.7 Analog-Front-End Controller (AFEC) User Interface Any offset not listed in Table 45-7 must be considered as “reserved”. Table 45-7.
Table 45-7.
45.7.1 AFEC Control Register Name: AFEC_CR Address: 0x400B0000 (0), 0x400B4000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 AUTOCAL 2 – 1 START 0 SWRST SWRST: Software Reset 0: No effect. 1: Resets the AFEC simulating a hardware reset. START: Start Conversion 0: No effect. 1: Begins Analog-Front-End conversion.
45.7.2 AFEC Mode Register Name: AFEC_MR Address: 0x400B0004 (0), 0x400B4004 (1) Access: Read/Write 31 USEQ 30 – 29 23 ANACH 22 – 21 15 14 13 28 27 26 TRANSFER 25 24 17 16 TRACKTIM 20 19 18 SETTLING STARTUP 12 11 10 9 8 3 2 TRGSEL 1 0 TRGEN PRESCAL 7 FREERUN 6 FWUP 5 SLEEP 4 – This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
FWUP: Fast Wake-up Value Name Description 0 OFF Normal Sleep Mode: The sleep mode is defined by the SLEEP bit 1 ON Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and AFEC Core is OFF FREERUN: Free Run Mode Value Name Description 0 OFF Normal Mode 1 ON Free Run Mode: Never wait for any trigger.
SETTLING: Analog Settling Time Value Name Description 0 AST3 3 periods of AFEClock 1 AST5 5 periods of AFEClock 2 AST9 9 periods of AFEClock 3 AST17 17 periods of AFEClock ANACH: Analog Change Value Name Description 0 NONE No analog change on channel switching: DIFF0, GAIN0 are used for all channels 1 ALLOWED Allows different analog settings for each channel. See AFEC_CGR. TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) * AFEClock periods.
45.7.3 AFEC Extended Mode Register Name: AFEC_EMR Address: 0x400B0008 (0), 0x400B4008 (1) Access: Read/Write 31 – 30 – 29 23 – 22 – 21 15 – 14 – 13 7 6 5 CMPSEL 28 27 – 26 – 25 STM 24 TAG 20 19 – 18 17 RES 16 12 11 – 10 – 9 CMPALL 8 – 4 3 2 – 1 0 SIGNMODE AFEMODE CMPFILTER CMPMODE This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
Value Name Description 3 OSR16 14-bit resolution, AFEC sample rate divided by 16 (averaging). 4 OSR64 15-bit resolution, AFEC sample rate divided by 64 (averaging). 5 OSR256 16-bit resolution, AFEC sample rate divided by 256 (averaging). AFEMODE: AFE Running Mode Value Name 0 NORMAL 1 OFFSET_ERROR 2 GAIN_ERROR_HIGH 3 GAIN_ERROR_LOW Description Normal mode of operation. Offset Error mode to measure the offset error. Gain Error mode to measure the gain error.
45.7.4 AFEC Channel Sequence 1 Register Name: AFEC_SEQ1R Address: 0x400B000C (0), 0x400B400C (1) Access: Read/Write 31 30 29 28 27 26 USCH7 23 22 21 20 19 18 USCH5 15 14 13 6 24 17 16 9 8 1 0 USCH4 12 11 10 USCH3 7 25 USCH6 USCH2 5 4 USCH1 3 2 USCH0 This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
45.7.5 AFEC Channel Sequence 2 Register Name: AFEC_SEQ2R Address: 0x400B0010 (0), 0x400B4010 (1) Access: Read/Write 31 30 29 28 27 26 USCH15 23 22 21 20 19 18 USCH13 15 14 13 6 24 17 16 9 8 1 0 USCH12 12 11 10 USCH11 7 25 USCH14 USCH10 5 4 USCH9 3 2 USCH8 This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
45.7.6 AFEC Channel Enable Register Name: AFEC_CHER Address: 0x400B0014 (0), 0x400B4014 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
45.7.7 AFEC Channel Disable Register Name: AFEC_CHDR Address: 0x400B0018 (0), 0x400B4018 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register. CHx: Channel x Disable 0: No effect.
45.7.8 AFEC Channel Status Register Name: AFEC_CHSR Address: 0x400B001C (0), 0x400B401C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 CHx: Channel x Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled.
45.7.9 AFEC Last Converted Data Register Name: AFEC_LCDR Address: 0x400B0020 (0), 0x400B4020 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 23 – 22 – 21 – 20 – 19 – 15 14 13 12 26 25 24 18 – 17 – 16 – 11 10 9 8 3 2 1 0 CHNB LDATA 7 6 5 4 LDATA LDATA: Last Data Converted The Analog-Front-End conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
45.7.10 AFEC Interrupt Enable Register Name: AFEC_IER Address: 0x400B0024 (0), 0x400B4024 (1) Access: Write-only 31 EOCAL 30 TEMPCHG 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect.
45.7.11 AFEC Interrupt Disable Register Name: AFEC_IDR Address: 0x400B0028 (0), 0x400B4028 (1) Access: Write-only 31 EOCAL 30 TEMPCHG 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect.
45.7.
45.7.13 AFEC Interrupt Status Register Name: AFEC_ISR Address: 0x400B0030 (0), 0x400B4030 (1) Access: Read-only 31 EOCAL 30 TEMPCHG 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 EOCx: End of Conversion x 0: The corresponding analog channel is disabled, or the conversion is not finished.
EOCAL: End of Calibration Sequence 0: Calibration sequence is on going, or no calibration sequence has been requested. 1: Calibration sequence is complete.
45.7.14 AFEC Overrun Status Register Name: AFEC_OVER Address: 0x400B004C (0), 0x400B404C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 OVRE15 14 OVRE14 13 OVRE13 12 OVRE12 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 OVREx: Overrun Error x 0: No overrun error on the corresponding channel since the last read of AFEC_OVER.
45.7.15 AFEC Compare Window Register Name: AFEC_CWR Address: 0x400B0050 (0), 0x400B4050 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 HIGHTHRES 23 22 21 20 HIGHTHRES 15 14 13 12 LOWTHRES 7 6 5 4 LOWTHRES This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register. LOWTHRES: Low Threshold Low threshold associated to compare settings of the AFEC_EMR.
45.7.16 AFEC Channel Gain Register Name: AFEC_CGR Address: 0x400B0054 (0), 0x400B4054 (1) Access: Read/Write 31 30 29 GAIN15 23 22 21 GAIN11 15 27 14 20 13 19 6 12 5 25 24 GAIN12 18 17 GAIN9 11 GAIN6 GAIN3 26 GAIN13 GAIN10 GAIN7 7 28 GAIN14 10 9 GAIN5 4 GAIN2 3 16 GAIN8 8 GAIN4 2 1 GAIN1 0 GAIN0 This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
45.7.17 AFEC Channel Calibration DC Offset Register Name: AFEC_CDOR Address: 0x400B005C (0), 0x400B405C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 OFF15 14 OFF14 13 OFF13 12 OFF12 11 OFF11 10 OFF10 9 OFF9 8 OFF8 7 OFF7 6 OFF6 5 OFF5 4 OFF4 3 OFF3 2 OFF2 1 OFF1 0 OFF0 This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
45.7.18 AFEC Channel Differential Register Name: AFEC_DIFFR Address: 0x400B0060 (0), 0x400B4060 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DIFF15 14 DIFF14 13 DIFF13 12 DIFF12 11 DIFF11 10 DIFF10 9 DIFF9 8 DIFF8 7 DIFF7 6 DIFF6 5 DIFF5 4 DIFF4 3 DIFF3 2 DIFF2 1 DIFF1 0 DIFF0 This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
45.7.19 AFEC Channel Selection Register Name: AFEC_CSELR Address: 0x400B0064 (0), 0x400B4064 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 3 2 1 0 CSEL CSEL: Channel Selection 0–15: Selects the channel to be displayed in the AFEC_CDR and AFEC_CAOR. To be filled with the appropriate channel number.
45.7.20 AFEC Channel Data Register Name: AFEC_CDR Address: 0x400B0068 (0), 0x400B4068 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA DATA: Converted Data Returns the Analog-Front-End conversion data corresponding to channel CSEL (configured in the AFEC Channel Selection Register).
45.7.21 AFEC Channel Offset Compensation Register Name: AFEC_COCR Address: 0x400B006C (0), 0x400B406C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 AOFF 3 2 AOFF AOFF: Analog Offset Defines the analog offset to be used for channel CSEL (configured in the AFEC Channel Selection Register). This value is used as input value for the DAC included in the AFEC.
45.7.22 AFEC Temperature Sensor Mode Register Name: AFEC_TEMPMR Address: 0x400B0070 (0), 0x400B4070 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 4 TEMPCMPMOD 3 – 2 – 1 – 0 RTCT RTCT: Temperature Sensor RTC Trigger mode 0: The temperature sensor measure is not triggered by RTC event. 1: The temperature sensor measure is triggered by RTC event (if TRGEN = 1).
45.7.23 AFEC Temperature Compare Window Register Name: AFEC_TEMPCWR Address: 0x400B0074 (0), 0x400B4074 (1) Access: Read/Write 31 30 29 28 27 THIGHTHRES 26 25 24 23 22 21 20 19 THIGHTHRES 18 17 16 15 14 13 12 11 10 9 8 3 2 1 0 TLOWTHRES 7 6 5 4 TLOWTHRES This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register. TLOWTHRES: Temperature Low Threshold Low threshold associated to compare settings of the AFEC_TEMPMR.
45.7.24 AFEC Analog Control Register Name: AFEC_ACR Address: 0x400B0094 (0), 0x400B4094 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 8 IBCTL 0 – This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register. IBCTL: AFEC Bias Current Control Allows to adapt performance versus power consumption.
45.7.25 AFEC Write Protection Mode Register Name: AFEC_WPMR Address: 0x400B00E4 (0), 0x400B40E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN WPEN: Write Protection Enable 0 = Disables the write protection if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1 = Enables the write protection if WPKEY corresponds to 0x414443 (“ADC” in ASCII). See Section 45.6.
45.7.26 AFEC Write Protection Status Register Name: AFEC_WPSR Address: 0x400B00E8 (0), 0x400B40E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the AFEC_WPSR. 1: A Write Protect Violation has occurred since the last read of the AFEC_WPSR.
46. Digital-to-Analog Converter Controller (DACC) 46.1 Description The Digital-to-Analog Converter Controller (DACC) provides up to 2 analog outputs, making it possible for the digital-to-analog conversion to drive up to 2 independent analog lines. The DACC supports 12-bit resolution. Data to be converted are sent in a common register for all channels. External triggers or free-running mode are configurable. 46.
46.3 Block Diagram Figure 46-1.
46.4 Signal Description Table 46-1. 46.5 DACC Pin Description Pin Name Description DAC0–DAC1 Analog output channels DATRG External triggers Product Dependencies 46.5.1 Power Management The user must first enable the DAC Controller Clock in the Power Management Controller (PMC) before using the DACC. The DACC becomes active as soon as a conversion is requested and at least one channel is enabled. The DACC is automatically deactivated when no channels are enabled.
46.6 Functional Description 46.6.1 Digital-to-Analog Conversion The DACC uses the peripheral clock divided by either two or four to perform conversions. This clock is named DAC clock. If the peripheral clock frequency is above 100 MHz, the CLKDIV bit must be set in the DACC Mode Register (DACC_MR). Once a conversion starts, the DACC takes 25 clock periods to provide the analog result on the selected analog output. 46.6.
46.6.6 DACC Timings The DACC start-up time must be defined by the user in the STARTUP field of the DACC_MR. A maximum speed mode is available by setting the MAXS bit in the DACC_MR. In this mode, the DACC no longer waits to sample the end-of-cycle signal coming from the DACC block to start the next conversion. An internal counter is used instead, thus gaining two peripheral clock periods between each consecutive conversion.
46.7 Digital-to-Analog Converter Controller (DACC) User Interface Table 46-3.
46.7.
46.7.2 DACC Mode Register Name: DACC_MR Address: 0x400B8004 Access: Read/Write 31 – 30 – 29 28 23 – 22 CLKDIV 21 MAXS 20 TAG 15 – 14 – 13 – 7 – 6 – 5 – 27 26 25 24 19 – 18 – 17 12 – 11 – 10 – 9 – 8 ONE 4 WORD 3 2 TRGSEL 1 0 TRGEN STARTUP 16 USER_SEL This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register. • TRGEN: Trigger Enable Value Name Description 0 DIS External trigger mode disabled. DACC in free-running mode.
• TAG: Tag Selection Mode Value Name Description 0 DIS Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.
Value Name Description 23 1472 1472 periods of peripheral clock 24 1536 1536 periods of peripheral clock 25 1600 1600 periods of peripheral clock 26 1664 1664 periods of peripheral clock 27 1728 1728 periods of peripheral clock 28 1792 1792 periods of peripheral clock 29 1856 1856 periods of peripheral clock 30 1920 1920 periods of peripheral clock 31 1984 1984 periods of peripheral clock 32 2048 2048 periods of peripheral clock 33 2112 2112 periods of peripheral clock 34
Value Name Description 61 3904 3904 periods of peripheral clock 62 3968 3968 periods of peripheral clock 63 4032 4032 periods of peripheral clock Note: Refer to the DAC electrical characteristics section in the datasheet for start-up time value.
46.7.3 DACC Channel Enable Register Name: DACC_CHER Address: 0x400B8010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
46.7.4 DACC Channel Disable Register Name: DACC_CHDR Address: 0x400B8014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
46.7.
46.7.6 DACC Conversion Data Register Name: DACC_CDR Address: 0x400B8020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Convert When the WORD bit in DACC_MR is cleared, only DATA[15:0] is used; else DATA[31:0] is used to write two data to be converted.
46.7.
46.7.8 DACC Interrupt Disable Register Name: DACC_IDR Address: 0x400B8028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt • TXRDY: Transmit Ready Interrupt Disable.
46.7.
46.7.10 DACC Interrupt Status Register Name: DACC_ISR Address: 0x400B8030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY • TXRDY: Transmit Ready Interrupt Flag 0: DACC is not ready to accept new conversion requests. 1: DACC is ready to accept new conversion requests.
46.7.11 DACC Analog Current Register Name: DACC_ACR Address: 0x400B8094 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 IBCTLDACCORE 7 – 6 – 5 – 4 – 3 2 1 IBCTLCH1 0 IBCTLCH0 This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
46.7.12 DACC Write Protection Mode Register Name: DACC_WPMR Address: 0x400B80E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x444143 (“DAC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x444143 (“DAC” in ASCII). See Section 46.6.
46.7.13 DACC Write Protection Status Register Name: DACC_WPSR Address: 0x400B80E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the DACC_WPSR. 1: A write protection violation has occurred since the last read of the DACC_WPSR.
47. SAM4E Electrical Characteristics 47.1 Absolute Maximum Ratings Table 47-1. Absolute Maximum Ratings* Operating Temperature (Industrial)..................-40°C to + 105°C *NOTICE: Storage Temperature......................................-60°C to + 150°C Voltage on Input Pins with Respect to Ground......................................-0.3V to + 4.0V Maximum Operating Voltage (VVDDCORE)....................................................................1.
47.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 105°C, unless otherwise specified. Table 47-2. Symbol DC Characteristics Parameter Conditions Min Typ Max Units VVDDCORE DC Supply Core — 1.08 1.20 1.32 V VVDDIO DC Supply I/Os (2) (3) 1.62 3.3 3.6 V VVDDPLL PLL A and Main Oscillator Supply — 1.08 — 1.32 V VIL Low-level Input Voltage PA0-PA31, PB0-PB14, PC0-PC31, PD0-PD31, PE0-PE5 -0.3 — MIN [0.8V,0.
Table 47-2. Symbol DC Characteristics (Continued) Parameter Conditions Min Typ Max PA14 (SPCK), PA29 (MCCK) pins — — 4 PA[5:8], PA[12-13], PA[26-28], PA[30-31], PB[8:9], PB[14], PD[0:1], PD[3:17] pins — — 4 PA [0-3] — — 2 Other pins — — 2 VDDIO [3.0V : 3.60V] PB[10-11] — — 30 VDDIO [1.62V : 3.60V]; VOL = 0.
Table 47-3. Symbol 1.2V Voltage Regulator Characteristics Parameter Conditions Min Typ Max Units VVDDIN DC Input Voltage Range (4) (5) 1.6 3.3 3.6 V VVDDOUT DC Output Voltage Normal Mode — 1.2 — Standby Mode — 0 — VACCURACY Output Voltage Accuracy ILoad = 0.8 mA to 80 mA (after trimming) -4 ILOAD Maximum DC Output Current VVDDIN > 1.8V — — 120 VVDDIN ≤ 1.8V — — 70 400 4 ILOAD-START Maximum Peak Current during startup (3) — — DDROPOUT Dropout Voltage VVDDIN = 1.
Table 47-4. Symbol Core Power Supply Brownout Detector Characteristics Parameter Conditions (1) Min Typ Max Units VTH- Supply Falling Threshold — 0.98 1.0 1.04 V VHYST Hysteresis — — — 110 mV VTH+ Supply Rising Threshold — 0.8 1.0 1.
Table 47-5. VDDIO Supply Monitor Symbol Parameter Conditions Min Typ Max Units VTH Supply Monitor Threshold 16 selectable steps 1.6 — 3.4 V TACCURACY Accuracy threshold level -40/+105°C -2.5 — +2.5 % VHYST Hysteresis — 20 30 mV Enabled — 23 40 Disabled — 0.02 2 From disabled state to enabled state — — 300 IDDON µA Current Consumption IDDOFF tSTART Startup Time Table 47-6.
Figure 47-2. VDDIO Supply Monitor VDDIO VTH + VHYST VTH Reset Table 47-7. Zero-Power-On Reset Characteristics Symbol Parameter Conditions Min Typ Max Units VTH+ Threshold voltage rising At Startup 1.45 1.53 1.59 V VTH- Threshold voltage falling — 1.35 1.45 1.55 V tRES Reset Time-out Period — 100 340 580 µs Typ Max Units 16 25 mA 10 18 mA 3 5 mA Figure 47-3. Zero-Power-On Reset Characteristics VDDIO VTH+ VTH- Reset Table 47-8.
47.3 Power Consumption Power consumption of the device depending on the different Low-Power mode Capabilities (Backup, Wait, Sleep) and Active mode. Power consumption on power supply in different modes: Backup, Wait, Sleep and Active. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. All power consumption values are based on characterization.
Table 47-9. Typical Power Consumption for Backup Mode Configuration A and B Typical value BACKUP Total Consumption @25°C @85°C @105°C Conditions (AMP1) Configuration A (AMP1) Configuration B (AMP1) Configuration A (AMP1) Configuration A VVDDIO = 3.6V 2.0 1.9 7.2 15.4 VVDDIO = 3.3V 1.7 1.6 6.9 12.0 VVDDIO = 3.0V 1.5 1.5 6.2 11.2 VVDDIO = 2.5V 1.3 1.2 5.5 9.8 VVDDIO = 1.8V 1 0.9 4.6 8.3 Unit µA 47.3.
Figure 47-6. Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (Condition from Table 47-10) 10,000 8,000 6,000 AMP1 VDDCORE (mA) 4,000 2,000 0,000 0 Table 47-10. 30 40 50 60 70 80 90 Processor and Peripheral Clocks in MHz 100 110 120 VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit 120 9.8 11.4 mA 100 8.2 9.5 mA 84 7.1 9.4 mA 64 5.5 7.2 mA 48 4.2 5.5 mA 32 3.0 4.7 mA 24 2.3 3.
Table 47-11. Sleep Mode Current Consumption versus Master Clock (MCK) Variation with FAST RC VDDCORE Consumption (AMP1) Core Clock/MCK (MHz) Total Consumption (AMP2) Unit 1 0.22 0.25 mA 0.5 0.18 0.21 mA 0.25 0.16 0.19 mA 47.3.2.2 Wait Mode Figure 47-7. Measurement Setup for Wait Mode AMP2 3.6V VDDIO VDDIN AMP1 Voltage Regulator VDDOUT VDDCORE VDDPLL VVDDIO = VVDDIN = 3.
47.3.3 Active Mode Power Consumption The Active Mode configuration and measurements are defined as follows: VVDDIO = VVDDIN = 3.3V VVDDCORE = 1.2V (Internal Voltage regulator used) TA = 25°C Application Running from Flash Memory with 128-bit access Mode All Peripheral clocks are deactivated. Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator. Current measurement on AMP1 (VDDCORE) and total current on AMP2 Figure 47-8.
47.3.3.1 SAM4E Active Power Consumption Table 47-13. Active Power Consumption with VDDCORE @ 1.2V running from Embedded Memory (IDDCORE- AMP1) Core Mark Cache Enable (CE) Cache Disable (CD) Core Clock (MHz) 128-bit Flash access(1) 64-bit Flash access(1) 128-bit Flash access(1) 64-bit Flash access(1) SRAM 120 21.1 21.0 25.5 19.0 17.9 100 18.1 18.1 22.5 17.2 15.0 84 15.5 15.5 20.0 16.1 12.86 64 11.9 11.9 16.4 13.6 9.9 48 9.0 9.0 12.7 11.7 7.5 32 6.2 6.2 9.1 8.9 5.
47.3.3.2 SAM4E Active Total Power Consumption Table 47-14. Active Total Power Consumption with VDDCORE @ 1.2V running from Embedded Memory (IDDIO + IDDIN AMP2) CoreMark Cache Enable (CE) Core Clock (MHz) Note: Cache Disable (CD) 128-bit Flash Access(1) 64-bit Flash Access(1) 128-bit Flash Access(1) 64-bit Flash Access(1) SRAM 120 22.6 22.6 29.2 22.3 19.5 100 19.5 19.5 25.7 20.2 16.4 84 17.7 17.8 24.0 19.9 15.1 64 13.6 13.6 19.7 16.7 11.5 48 10.3 10.3 14.7 14.4 8.
47.3.4 Peripheral Power Consumption in Active Mode Table 47-15. Power Consumption on VDDCORE (1) Peripheral Consumption (Typ) PIO Controller A (PIOA) 5.23 PIO Controller B (PIOB) 1.44 PIO Controller C (PIOC) 4.02 PIO Controller D (PIOD) 3.17 PIO Controller E (PIOE) 0.86 UART 4.50 USART 6.5 PWM 11.00 TWI 4.70 SPI 4.42 Timer Counter (TCx) 3.7 AFEC 5.15 DACC 3.0 ACC 0.28 HSMCI 6.43 CAN 6.5 SMC 2.77 UDP 5.11 EMAC 44.2 AES 2.39 DMAC 7.21 Note: 1.
47.4 Oscillator Characteristics 47.4.1 32 kHz RC Oscillator Characteristics Table 47-16.
47.4.3 32.768 kHz Crystal Oscillator Characteristics Table 47-18. 32.768 kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fREQ Operating Frequency Normal mode with crystal — — 32.768 kHz — Supply Ripple Voltage (on VDDIO) Rms value, 10 kHz to 10 MHz — — 30 mV — Duty Cycle 40 50 60 % Ccrystal = 12.5 pF — — 900 Rs < 50 kΩ — Startup Time Current consumption IDDON Ccrystal = 6 pF — — 300 Rs < 100 kΩ Ccrystal = 12.
47.4.4 32.768 kHz Crystal Characteristics Table 47-19. Crystal Characteristics Symbol Parameter Conditions Min Typ Max Unit ESR Equivalent Series Resistor (RS) Crystal @ 32.768 kHz — 50 100 kΩ CM Motional capacitance Crystal @ 32.768 kHz 0.6 — 3 fF CSHUNT Shunt capacitance Crystal @ 32.768 kHz 0.6 — 2 pF 47.4.5 3 to 20 MHz Crystal Oscillator Characteristics Table 47-20.
Figure 47-12. 3 to 20 MHz Crystal Oscillator Schematics SAM4 CL XOUT XIN R = 1kΩ if Crystal Frequency is lower than 8 MHz CCRYSTAL CLEXT CLEXT CLEXT = 2x(CCRYSTAL – CL – CPCB) where: CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin. 47.4.6 3 to 20 MHz Crystal Characteristics Table 47-21.
47.4.8 Crystal Oscillator Design Considerations Information 47.4.8.1 Choosing a Crystal When choosing a crystal for the 32.768 kHz Slow Clock Oscillator or for the 3-20 MHz Oscillator, several parameters must be taken into account. Important parameters between crystal and SAM4E specifications are as follows: Load Capacitance ̶ CCRYSTAL is the equivalent capacitor value the oscillator must “show” to the crystal in order to oscillate at the target frequency.
47.6 USB Transceiver Characteristics 47.6.1 Typical Connection For typical connection please refer to the USB Device Section. 47.6.2 Electrical Characteristics Table 47-25. Symbol Electrical Parameters Parameter Conditions Min Typ Max Unit Input Levels VIL Low Level — — — 0.8 V VIH High Level — 2.0 — — V VDI Differential Input Sensitivity 0.2 — — V VCM Differential Input Common Mode Range 0.8 — 2.
47.6.3 Switching Characteristics Table 47-26. In Full Speed Symbol Parameter Conditions Min Typ Max Unit tr Transition Rise Time CLOAD = 50 pF 4 — 20 ns tf Transition Fall Time CLOAD = 50 pF 4 — 20 ns trfm Rise/Fall time Matching — 90 — 111.11 % Figure 47-13.
47.7 12-bit AFE (Analog Front End) Characteristics Electrical data are in accordance with the following standard conditions unless otherwise specified: Operating temperature range from -40°C to + 105°C Min and max data are defined as three times the standard deviation of the manufacturing process Figure 47-14.
47.7.2 External Reference Voltage VADVREF is an external reference voltage applied on the pin ADVREF. The quality of the reference voltage VADVREF is critical to the performance of the ADC. A DC variation of the reference voltage VADVREF is converted to a gain error by the ADC. The noise generated by VADVREF is converted by the ADC to count noise. Table 47-29. ADVREF Electrical Characteristics Symbol Parameter VADVREF ADVREF voltage range Conditions Min Typ Max Full operational 2.4 — 3.
47.7.4 ADC Transfer Function The first operation of the ADC is a sampling function relative to a common mode voltage. The common mode voltage (VCM) is equal to VADVREF/2 when the bits OFFx = 1, in Differential and in Single-ended mode. When the bits OFFx = 0, sampling is done versus VADVREF/4 for gain = 2, and VADVREF/8 for gain = 4, in Single-ended mode only. The code in AFEC_CDR is a 12-bit positive integer. The internal DAC is set for the code 2047. 47.7.4.
Table 47-33 is a computation example for the above formula, where VADVREF = 3V: Table 47-33. Input Voltage Values in Single-ended Mode, OFFx=0 Ci Gain = 1 Gain = 2 Gain = 4 0 0 0 0 2047 1.5 0.75 0.375 4095 3 1.5 0.75 47.7.4.3 Example of LSB Computation The LSB is relative to the analog scale VADVREF. The term LSB expresses the quantization step in volts, also used for one ADC code variation. Single-ended (SE) (ex: VADVREF=3.0V) ̶ Gain = 1, LSB = (3.
Differential Mode In differential mode, the offset is defined when the differential input voltage is zero. Figure 47-15.
Single-ended Mode Figure 47-16 illustrates the ADC output code relative to an input voltage VIN between 0V (Ground) and VADVREF. The ADC is configured in Single-ended mode by connecting internally the negative differential input to VADVREF/2. As the ADC continues to work internally in Differential mode, the offset is measured at VADVREF/2. Figure 47-16.
Table 47-38. Single-ended Output Offset Error Standard Deviation (LSB) 1.8 3.9 3.4 6 7 Min Value (LSB) -11.1 -19.4 -20.5 -25.3 -39.7 Max Value (LSB) -0.3 4 -0.1 10.7 2.3 47.7.5.2 ADC Electrical Performances Single-ended Static Performances Table 47-39. Single-ended Static Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit INL ADC Integral Non-linearity — -2 +/-1 2 LSB DNL ADC Differential Non-linearity — -1 -+/-0.
The dynamic performances are the 12-bit mode values, reduced by 12 dB. Low Voltage Supply The ADC operates in 10-bit mode or 12-bit mode. Working at low voltage (VDDIN or/and VADVREF) between 2 and 2.4V is subject to the following restrictions: The field IBCTL must be 00 to reduce the biasing of the ADC under low voltage. See Section 47.7.1.1 “ADC Bias Current”. In 10-bit mode, the ADC clock should not exceed 5 MHz (max signal bandwidth is 250 kHz).
Table 47-43. Note: Input Capacitance (CIN) Values 1 2 pF 4 pF 2 2 pF 8 pF 4 4 pF 1. N/A: Not applicable N/A Table 47-44. ZIN Input Impedance fS (MHz) 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 8 16 32 64 4 8 16 32 2 4 8 16 CIN = 2 pF ZIN (MΩ) 0.5 1 2 4 CIN = 4 pF ZIN (MΩ) 0.25 0.5 1 2 CIN = 8 pF ZIN (MΩ) 0.125 0.25 0.5 1 Track and Hold Time versus Source Output Impedance Figure 47-18 shows a simplified acquisition path. Figure 47-18.
Table 47-45.
47.7.6 ADC Resolution with Averaging 47.7.6.1 Conditions @ 25°C with Gain =1 fADC = 20 MHz; fADC = 2 MHz for INL and DNL static measurement only fS = 1 MHz, ADC Sampling Frequency in Free Run Mode VADVREF = 3V Signal Amplitude: VADVREF/2, Signal Frequency < 100 Hz OSR: Number of Averaged Samples VVDDIN = 2.4V Table 47-46.
47.7.6.2 Conditions @ 25°C with Gain =4 fADC = 20 MHz fS = 1 MHz, ADC Sampling Frequency in Free Run Mode VADVREF= 3V Signal Amplitude: VADVREF/2, Signal Frequency < 100 Hz OSR: Number of Averaged Samples Table 47-47. ADC Resolution following Digital Averaging (Gain=4) Parameter Averaging Resolution RES (AFEC_EMR) Over Sampling Ratio Mode (bits) INL (LSB) DNL (LSB) SNR (dB) THD (dB) ENOB (Bits) FS (ksps) Single Ended Mode RES = 0 1 12 +/-1 +/-0.5 59 -81 9.
47.8 12-bit DAC Characteristics Table 47-48. Analog Power Supply Characteristics Symbol Parameter Conditions VVDDIN Analog Supply — 2.4 3.0 3.6 V Sleep Mode (Clock OFF) — — 3 µA Fast Wake-up (Standby Mode, Clock on) — 2 3 mA Normal Mode with 1 Output ON (IBCTLDACCORE = 01, IBCTLCHx =10) — 4.3 5.6 mA Normal Mode with 2 Outputs ON (IBCTLDACCORE =01, IBCTLCHx =10) — 5 6.5 mA Min Typ Max Units Current Consumption IVDDIN Table 47-49.
Table 47-51. Dynamic Performance Characteristics Parameter Conditions Min Typ Max 2.4V < VVDDIN <2.7V 47 58 70 dB Signal to Noise Ratio - SNR 2.7V < VVDDIN <3.6V 56 61 74 2.4V < VVDDIN <2.7V — -72 -60 dB Total Harmonic Distortion - THD 2.7V < VVDDIN <3.6V — -76 -68 2.4V < VVDDIN <2.7V 47 58 — Signal to Noise and Distortion - SINAD dB 2.7V < VVDDIN <3.6V 56 61 — 2.4V < VVDDIN <2.7V 7.5 9 12 2.7V < VVDDIN <3.6V 9 10 12 bits Effective Number of Bits ENOB Table 47-52.
47.9 Analog Comparator Characteristics Table 47-53. Analog Comparator Characteristics Parameter Conditions Min Typ Max Units Voltage Range The Analog Comparator is supplied by VDDIN 1.62 3.3 3.6 V Input Voltage Range — GND + 0.2 — VVDDIN - 0.2 V Input Offset Voltage — — — 20 mV Low Power Option (ISEL = 0) — — 25 µA High Speed Option (ISEL = 1) — — 170 HYST = 0x01 or 0x10 — 15 50 HYST = 0x11 — 30 90 Low Power Option — — 1 High Speed Option — — 0.
47.11 AC Characteristics 47.11.1 Master Clock Characteristics Table 47-55. Master Clock Waveform Parameters Symbol Parameter Conditions Min Max Units 1/(tCP_MCK) Master Clock Frequency VDDCORE @ 1.20V — 120 MHz 1/(tCP_MCK) Master Clock Frequency VDDCORE @ 1.08V — 100 MHz 47.11.
47.11.3 SPI Characteristics Figure 47-19. SPI Master Mode with (CPOL= NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 47-20. SPI Master Mode with (CPOL = 0 and NCPHA=1) or (CPOL=1 and NCPHA= 0) SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 47-21.
Figure 47-22. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) NPCS0 SPI15 SPI14 SPCK SPI9 MISO SPI10 SPI11 MOSI 47.11.3.1 Maximum SPI Frequency The following formulas give the maximum SPI frequency in Master read and write modes and in Slave read and write modes. Master Write Mode The SPI only sends data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing. Since it gives a maximum frequency above the pin FreqMax value (see Section 47.11.
47.11.3.2 SPI Timings Table 47-57.
47.11.4 HSMCI Timings The High Speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1. 47.11.5 SMC Timings Timings are given in the following domains: 1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF 3.3V domain: VVDDIO from 2.85V to 3.6V, maximum external capacitor = 50 pF.
Table 47-59. Symbol — SMC Read Signals - NCS Controlled (READ_MODE= 0) Parameter Min VDDIO supply 1.8V (1) Max (2) (1) 3.3V Units (2) 1.8V 3.3V — NO HOLD SETTINGS (NCS RD hold = 0) SMC8 Data Setup before NCS High SMC9 Data Hold after NCS High 21.8 19.4 — — ns 0 0 — — ns 17.1 14.
47.11.5.2 Write Timings Table 47-60. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Min Symbol Parameter 1.8V Max (2) 3.3V (3) (2) 1.8V 3.3V(3) Units HOLD or NO HOLD SETTINGS (NWE hold ≠ 0, NWE hold = 0) SMC15 Data Out Valid before NWE High NWE pulse * tCP_MCK - 6.2 NWE pulse * tCP_MCK - 5.9 — — ns SMC16 NWE Pulse Width NWE pulse * tCP_MCK - 7.0 NWE pulse * tCP_MCK - 6.1 — — ns SMC17 A0 - A22 valid before NWE low NWE setup * tCP_MCK - 6.6 NWE setup * tCP_MCK - 6.
Table 47-61. SMC Write NCS Controlled (WRITE_MODE = 0) Parameter Min 1.8V(1) 3.3V(2) NCS wr pulse * tCP_MCK NCS wr pulse * tCP_MCK - 6.3 - 6.0 NCS wr pulse * tCP_MCK NCS wr pulse * tCP_MCK - 7.6 - 6.7 NCS wr setup * tCP_MCK NCS wr setup * tCP_MCK - 6.7 - 6.3 (NCS wr setup - NWE setup + NCS pulse) * tCP_MCK (NCS wr setup - NWE setup + NCS pulse) * tCP_MCK - 5.6 - 5.3 NCS wr hold * tCP_MCK NCS wr hold * tCP_MCK - 10.6 - 9.
Figure 47-24. SMC Timings - NRD Controlled Read and NWE Controlled Write SMC21 SMC17 SMC5 SMC5 SMC17 SMC19 A0-A23 SMC6 SMC21 SMC6 SMC18 SMC18 SMC20 NCS SMC7 SMC7 NRD SMC1 SMC2 SMC15 SMC21 SMC3 SMC15 SMC4 SMC19 DATA NWE SMC16 NRD Controlled READ with NO HOLD SMC16 NWE Controlled WRITE with NO HOLD NRD Controlled READ with HOLD NWE Controlled WRITE with HOLD 47.11.6 USART in SPI Mode Timings Timings are given in the following domains: 1.8V domain: VVDDIO from 1.65V to 1.
Figure 47-26. USART SPI Slave Mode (Mode 1 or 2) • The MOSI line drives the input pin RXD • The MISO line is driven by the output pin TXD • The SCK line drives the input pin SCK • The NSS line drives the input pin CTS NSS SPI13 SPI12 SCK SPI6 MISO SPI7 SPI8 MOSI Figure 47-27.
47.11.6.1 USART SPI TImings Table 47-62. Symbol USART SPI Timings Parameter Conditions Min Max Units MCK/6 — ns — ns — ns — ns Master Mode SPI0 SCK Period SPI1 Input Data Setup Time SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 Output Data Setup Time SPI5 Serial Clock to Chip Select Inactive 1.8V domain 3.3V domain 1.8V domain 0.5 * MCK + 3.3 3.3V domain 0.5 * MCK + 3.7 1.8V domain 1.5 * MCK + 0.8 3.3V domain 1.5 * MCK + 1.1 1.8V domain 1.
47.11.7 Two-wire Serial Interface Characteristics Table 47-63 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols refer to Figure 47-28. Table 47-63. Two-wire Serial Bus Requirements Symbol Parameter Condition Min Max Units VIL Low-level input voltage — -0.3 0.3 VVDDIO V VIH High-level input voltage — 0.7xVVDDIO VCC + 0.3 V VHYS Hysteresis of Schmitt Trigger Inputs — 0.150 — V VOL Low-level output voltage 3 mA sink current — 0.
Figure 47-28. Two-wire Serial Bus Timing tHIGH tof tLOW tr tLOW TWCK tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO TWD tBUF 47.11.8 Ethernet MAC (GMAC) Characteristics 47.11.8.1 Timing Conditions Table 47-64. Capacitance Load on data, clock pads Corner Supply MAX STH MIN 3.3V 20 pf 20 pf 0 pf 1.8V 20 pf 20 pf 0 pf These values may be product dependant and should be confirmed by the specification. 47.11.8.
47.11.8.3 MII Mode Table 47-66.
Figure 47-30.
47.11.9 Embedded Flash Characteristics The maximum operating frequency is given in Table 47-67, Table 47-68, Table 47-69 and Table 47-70, but it is limited by the Embedded Flash access time when the processor is fetching code out of it. These tables provide the device maximum operating frequency depending on the field FWS of the MC_FMR. This field defines the number of wait states required to access the Embedded Flash Memory. Table 47-67. Table 47-68. Table 47-69. Table 47-70.
Table 47-71. AC Flash Characteristics Parameter Program Cycle Time Conditions Min Typ Max Units Write page mode — 1.5 3 ms Erase page mode — 10 50 ms Erase block mode (by 4 Kbytes) — 50 200 ms Erase sector mode — 400 950 ms 200 — — ms Erase Pin Assertion Time Erase pin high Full Chip Erase 1 Mbyte 512 Kbytes — — 9 5.
48. SAM4E Mechanical Characteristics The SAM4E series devices are available in TFBGA100, LFBGA144, LQFP100, and LQFP144 packages. 48.1 100-ball TFBGA Package Drawing Figure 48-1. 100-ball TFBGA Package Drawing Table 48-1. Device and TFBGA Package Maximum Weight (Preliminary) SAM4E Table 48-2. 150 mg TFBGA Package Reference JEDEC Drawing Reference MO-275-DDAC-2 JESD97 Classification e8 Table 48-3.
48.2 144-ball LFBGA Package Drawing Figure 48-2. 144-ball LFBGA Package Drawing Table 48-4. Device and LFBGA Package Maximum Weight (Preliminary) SAM4E 200 Table 48-5. LFBGA Package Reference JEDEC Drawing Reference MS-275-EEAD-1 JESD97 Classification e8 Table 48-6. LFBGA Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
48.3 100-lead LQFP Package Drawing Figure 48-3. 100-lead LQFP Package Drawing Table 48-7. Device and LQFP Package Maximum Weight (Preliminary) SAM4E Table 48-8. 740 LQFP Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification e3 Table 48-9. mg LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
48.4 144-lead LQFP Package Drawing Figure 48-4. 144-lead LQFP Package Drawing Table 48-10. Device and LQFP Package Maximum Weight (Preliminary) SAM4E 900 Table 48-11. LQFP Package Reference JEDEC Drawing Reference MS-026-C JESD97 Classification e3 Table 48-12. LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
48.5 Soldering Profile Table 48-13 gives the recommended soldering profile from J-STD-020C. Table 48-13. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260°C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
49. Marking All devices are marked with the Atmel logo and the ordering code.
50. Ordering Information Table 50-1.
51. Errata on SAM4E Devices 51.1 Errata 51.1.1 Watchdog 51.1.1.1 Watchdog Not Stopped in Wait Mode When the Watchdog is enabled and the bit WAITMODE = 1 is used to enter wait mode, the watchdog is not halted. If the time spent in Wait Mode is longer than the Watchdog time-out, the device will be reset if Watchdog reset is enabled.
51.1.3 Flash 51.1.3.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State Flash read issues leading to wrong instruction fetch or incorrect data read may occur under the following operating conditions: VDDIO < 2.4V and Flash wait state(1) ≥ 1 If the core clock frequency does not require the use of the Flash wait state (2) (FWS = 0 in EEFC_FMR), or if only data reads are performed on the Flash (e.g.
52. Revision History In the tables that follow, the most recent version of the document appears first. Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history Doc. Date Changes Modified Title of the document (SAM4E Series) Changed structure of the document (order of sections: GMAC, DAC...) Ethernet MAC (EMAC) replaced with Ethernet MAC (GMAC) and EMAC signals replaced with GMAC signals throughout the document (example: GTXCK instead of ETXCK, etc.). Section 1.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 12.10.1.4 “SysTick Calibration Value Register”: updated register reset value; updated ‘TENMS’ and ‘SKEW’ field descriptions Section 12.12.2.1 “Coprocessor Access Control Register”: replaced ‘CPn’ field description with ‘CP10 and CP11’ field descriptions Section 12.12.2.3 “Floating-point Context Address Register”: updated ‘ADDRESS’ field description Section 12.12.2.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 17. “Watchdog Timer (WDT)” Figure 17-2, “Watchdog Behavior”, “WDT_CR = WDRSTT” replaced with “WDT_CR.WDRSTT=1” Section 18. “Reinforced Safety Watchdog Timer (RSWDT)” General formatting and editorial changes throughout Section 18.2 “Embedded Characteristics”: added bullet “Windowed Watchdog” Figure 18-2 “Watchdog Behavior” replaced “RSWDT_CR = WDRSTT” with “RSWDT_CR.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 23. “Cortex M Cache Controller (CMCC)” Modified access rights for “Cache Controller Monitor Configuration Register” and “Cache Controller Monitor Enable Register” Modified reset value for “Cache Controller Monitor Status Register” Removed reset values for write-only registers Section 24. “SAM-BA Boot Program for SAM4E Microcontrollers” Modified frequency values in Section 24.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 33. “Controller Area Network (CAN)” Minor editorial formatting changes throughout MCK replaced with Peripheral clock Section 33.6.3 “Interrupt” and Section 33.8.1 “CAN Controller Initialization”: Replaced 2 “AIC” occurences with “interrupt controller. Updated Section 33.9.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 36. “Two-wire Interface (TWI)” Minor editorial and formatting changes throughout Added “Register Write Protection” in Section 36.2 “Embedded Characteristics” Updated Figure 36-1, “Block Diagram” Updated Section 36.6 “Product Dependencies”, Section 36.7.3.5 “Master Receiver Mode”, Section 36.7.3.7 “Using the Peripheral DMA Controller (PDC)” Restructured Section 36.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 38. “Universal Synchronous Asynchronous Receiver Transmitter (USART)” Minor formatting and editorial changes throughout Replaced all references to ‘MCK’ with ’peripheral clock’ Modified Figure 38-1 “USART Block Diagram”: Removed ‘SLCK’. Added ‘Bus clock’. Section 38-2 “I/O Line Description”: removed sentences: ‘Note that it is not recommended to use the USART interrupt line in edge sensitive mode.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 39. “Timer Counter (TC)” Editorial and formatting changes throughout Master clock” or “MCK” replaced with “peripheral clock”. Removed references to FILTER bit (register bit 19 now reserved in Section 39.7.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 41. “High Speed MultiMedia Card Interface (HSMCI)” Minor formatting and editorial changes throughout Figure 41-1, “Block Diagram (4-bit configuration)”: added “(4-bit configuration)” to title; added missing note below figure Modified Section 41.8.1 “Command - Response Operation” Section 41.13 “Register Write Protection” changed title (was “Write Protection Registers”); revised content Section 41.14.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 44. “Analog Comparator Controller (ACC)” Updated Figure 44-1 “Analog Comparator Controller Block Diagram” Added Table 44-1 “List of analog inputs” Updated Table 44-2 “ACC Pin List” ADx analog inputs replaced with AFEx_ADx external analog data inputs Section 44.1 “Description”, Section 44.6.2 “Analog Settings” and Section 44.6.4 “Fault Mode”: Updated section for clarity.
Table 52-1. SAM4E Datasheet Rev. 11157D 12-Jun-14 Revision history (Continued) Doc. Date Changes Section 46. “Digital-to-Analog Converter Controller (DACC)” Editorial and formatting changes throughout. MCK or Master clock replaced with Peripheral clock. Removed references to Sleep mode and refresh period Renamed “Features” chapter as “Embedded Characteristics” Updated Section 46.2 “Embedded Characteristics”” In Section 46.7.
Table 52-2. Doc. Date SAM4E Datasheet Rev. 11157C 25-Jul-2013 Revision History Changes Introduction In “Features” : - added information on Two-wire Interface in Peripherals section and Wake-on-LAN for EMAC - changed operating temperature range to 105°C Updated Table 1-1 “Configuration Summary” with TWI information In Section 4.
Table 52-2. Doc. Date SAM4E Datasheet Rev. 11157C 25-Jul-2013 Revision History (Continued) Changes PMC: Section 30.1.4.2 “Slow Clock Crystal Oscillator”, replaced “...in MOSCSEL bit of CKGR_MOR,...” with “...in XTALSEL bit of SUPC_CR,...” in the last phrase of the 3d paragraph. Section 30.1.4.2 “Slow Clock Crystal Oscillator”, added references on the OSCSEL bit of PMC_SR in the 3d paragraph. Register names in Clock Generator: Replaced “PLL_MCKR” with “PMC_MCKR” and “PLL_SR” with “PMC_SR” in Section 30.1.5.
Table 52-2. Doc. Date SAM4E Datasheet Rev. 11157C 25-Jul-2013 Revision History (Continued) Changes Electrical Characteristics Operating temperature is extended to 105°C. Changed/updated in: - Table 46-1 “Absolute Maximum Ratings*” - Section 46.
Table 52-3. Doc. Date SAM4E Datasheet Rev. 11157B 25-April-2013 Revision History Changes Introduction: Updated the section structure and added references to 100-ball TFBGA and 100-lead LQFP packages in: - Section 1. “Features” - Table 1-1 “Configuration Summary” - Figure 2-1 “SAM4E 100-pin Block Diagram” - Section 4.1 “100-ball TFBGA Package and Pinout” - Section 4.
Table 52-3. Doc. Date SAM4E Datasheet Rev. 11157B 25-April-2013 Revision History (Continued) Changes RTC: Section 18.2 “Embedded Characteristics”, added a new bullet "Safety/Security features”, right indented the 2 following bullets. Section 18.5 “Functional Description”, added the last paragraph (“The RTC can generate...”). SUPC: Updated Figure 20-1 “Supply Controller Block Diagram”. Updated the 2-nd paragraph in Section 20.4.7.
Table 52-3. Doc. Date SAM4E Datasheet Rev. 11157B 25-April-2013 Revision History (Continued) Changes PIO: Section 33.5 “Functional Description”, added pull-down resistor and registers in Figure 33-5 “Input Glitch Filter Timing”. Section 33.7.46 “PIO Write Protect Mode Register”, replaced the WPKEY bitfield description with a table. Added missing dashes for reserved registers in Table 33-3 “Register Mapping”. Replaced “DIVx” with “DIV” in Section 33.7.29 “PIO Slow Clock Divider Debouncing Register”.
Table 52-3. Doc. Date SAM4E Datasheet Rev. 11157B 25-April-2013 Revision History (Continued) Changes AFEC: Fixed a typo in Section 43.7.25 “AFEC Write Protect Mode Register”: replaced ‘(“AFE” in ASCII)’ with ‘(“ADC” in ASCII)’ in the WPEN and WPKEY bitfield descriptions. Updated register tables (replaced bitfield data with “-” for bits from 16 to 23) in: - Section 43.7.6 “AFEC Channel Enable Register” - Section 43.7.7 “AFEC Channel Disable Register” - Section 43.7.
Table 52-3. Doc. Date SAM4E Datasheet Rev. 11157B 25-April-2013 Revision History (Continued) Changes Electrical Characteristics: Added references to 100-ball TFBGA and 100-lead LQFP packages in Table 46-1 “Absolute Maximum Ratings*”. Updated data in: - Table 46-2 “DC Characteristics” - Table 46-3 “1.2V Voltage Regulator Characteristics” - Section 46.3.1.2 “Configuration B: 32768 kHz Crystal Oscillator Enabled” - Section 46.3.2.1 “Sleep Mode” - Section 46.3.2.
Table 52-3. Doc. Date SAM4E Datasheet Rev. 11157B 25-April-2013 Revision History (Continued) Changes Replaced “RES = 1” with “RES = 0” in Table 46-30 “ADC Resolution following Digital Averaging”. Updated Table 46-33 “Gain and Error Offset, 12-bit Mode, VDDIN 2.4V to 3.6V Supply Voltage Conditions”. Section 46.7.1.2 “Conditions @ 25 degrees with Gain =4”, replaced “fS = 1 kHz” with “fS = 1 MHz”. Section 46.11.3.2 “SPI Timings”, updated for better presentation the paragraph “Note that in SPI master mode,...
Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.
12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 Cortex-M4 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Cortex-M4 Core Peripherals . .
18.4 18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Reinforced Safety Watchdog Timer (RSWDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 19. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 19.1 19.2 19.3 19.4 19.5 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.10 SMC NAND Flash Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 25.11 Write Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 25.12 Bus Matrix (MATRIX) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 26. DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30.5 30.6 30.7 30.8 30.9 30.10 30.11 30.12 30.13 30.14 30.15 30.16 30.17 Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SysTick Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35.6 35.7 35.8 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 36. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41.1 41.2 41.3 41.4 41.5 41.6 41.7 41.8 41.9 41.10 41.11 41.12 41.13 41.14 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46.1 46.2 46.3 46.4 46.5 46.6 46.7 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . .
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