Features • Core • • • • • • – ARM® Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit (MPU) – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank – From 16 to 48 Kbytes embedded SRAM with dual banks – 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines – Static Memory Controller (SMC): SRAM, NOR, NAND support.
1. SAM3U Description Atmel's SAM3U series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 96 MHz and features up to 256 Kbytes of Flash and up to 52 Kbytes of SRAM.
SAM3U Series 2.
TST PCK0 -PCK2 In-Circuit Emulator PLLA OSC 3-20 M SysTick Counter N V I C PMC SM BOD RC 32K FLASH 2x128 KBytes 1x128 KBytes 1x64 KBytes 8 GPBREG SHDN FWUP SUPC RTC VDDBU NRSTB ERASE NRST POR UT DO N DI VD VD S Flash Unique Identifier RTT PDC 4-channel 12-bit ADC 10-bit ADC RSTC NAND Flash SRAM (4KBytes) 5-layer AHB Bus Matrix SRAM0 32 KBytes 16 KBytes 8 KBytes SRAM1 16 KBytes 16 KBytes ROM 16 KBytes Peripheral DMA Controller Peripheral Bridge NCS0 NCS1 NRD NWE 4-Channel DMA St
SAM3U Series 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input Power 1.8V to 3.6V VDDOUT Voltage Regulator Output Power 1.8V VDDUTMII USB UTMI+ Interface Power Supply Power 3.0V to 3.
Table 3-1.
SAM3U Series Table 3-1.
Table 3-1.
SAM3U Series 4. Package and Pinout The SAM3U4/2/1E is available in 144-lead LQFP and 144-ball TFBGA packages. The SAM3U4/2/1C is available in 100-lead LQFP and 100-ball TFBGA packages. 4.1 4.1.1 SAM3U4/2/1E Package and Pinout 144-ball TFBGA Package Outline The 144-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 10 x 10 x 1.4 mm. Figure 4-1. Orientation of the 144-ball TFBGA Package TOP VIEW 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BALL A1 4.1.
4.1.3 144-lead LQFP Pinout Table 4-1.
SAM3U Series 4.1.4 144-ball TFBGA Pinout Table 4-2.
4.2 4.2.1 SAM3U4/2/1C Package and Pinout 100-lead LQFP Package Outline Figure 4-3. Orientation of the 100-lead LQFP Package 75 76 50 100 26 1 4.2.2 51 25 100-ball TFBGA Package Outline Figure 4-4.
SAM3U Series 4.2.3 100-lead LQFP Pinout Table 4-3.
4.2.4 100-ball TFBGA Pinout Table 4-4.
SAM3U Series 5. Power Considerations 5.1 Power Supplies The SAM3U product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals I/O lines; voltage ranges from 1.62V to 3.6V. • VDDIN pin: Powers the Voltage regulator • VDDOUT pin: It is the output of the voltage regulator. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.
Figure 5-1. Single Supply VDDBU VDDUTMI VDDANA VDDIO Main Supply (1.62V-3.6V) VDDIN Voltage Regulator VDDOUT VDDCORE VDDPLL Note: 16 Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable.
SAM3U Series Figure 5-2. Core Externally Supplied VDDBU VDDUTMI VDDANA Main Supply (1.62V-3.6V) VDDIO VDDIN Voltage Regulator VDDOUT VDDCORE Supply (1.62V-1.95V) VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable.
Figure 5-3. Backup Batteries Used FWUP SHDN Backup Batteries VDDBU VDDUTMI VDDANA VDDIO VDDIN Main Supply (1.62V-3.6V) Voltage Regulator VDDOUT VDDCORE VDDPLL Note: 18 Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable.
SAM3U Series 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 Low Power Modes The various low power modes of the SAM3U are described below: 5.5.
Entering Wait Mode: • Select the 4/8/12 MHz Fast RC Oscillator as Main Clock • Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR) • Execute the Wait-For-Event (WFE) instruction of the processor Note: 5.5.3 Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode. Depending on the user application, Waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions.
SAM3U Series 5.5.4 Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Table 5-1.
5.6 Wake-up Sources The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 5-4.
SAM3U Series 5.7 Fast Start-Up The SAM3U allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs. The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast startup signal to the Power Management Controller.
6. Input/Output Lines The SAM3U has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same GPIO line can be used whether it is in IO mode or used by the multiplexed peripheral. System I/Os are pins such as test pin, oscillators, erase pin, analog inputs or debug pins. With a few exceptions, the I/Os have input schmitt triggers.
SAM3U Series The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the SW-DP.
Even in all low power modes, asserting the pin will automatically start-up the chip and erase the Flash. 7. Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single cycle 32-bit multiply. • Hardware divide. • Thumb and Debug states. • Handler and Thread modes.
SAM3U Series 7.4 Matrix Slaves The Bus Matrix of the SAM3U manages 10 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. 7.
7.6 DMA Controller • Acting as one Matrix Master • Embeds 4 channels: – 3 channels with 8 bytes/FIFO for Channel Buffering – 1 channel with 32 bytes/FIFO for Channel Buffering • Linked List support with Status Write Back operation at End of Transfer • Word, HalfWord, Byte transfer support.
SAM3U Series The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): Table 7-5. 7.
8. Product Mapping Figure 8-1.
SAM3U Series 9. Memories The embedded and external memories are described below. 9.1 9.1.1 Embedded Memories Internal SRAM The SAM3U4 (256 KBytes internal Flash version) embeds a total of 48 Kbytes high-speed SRAM (32 Kbytes SRAM0 and 16 Kbytes SRAM1). The SAM3U2 (128 KBytes internal Flash version) embeds a total of 32 Kbytes high-speed SRAM (16 Kbytes SRAM0 and 16 Kbytes SRAM1). The SAM3U1 (64 KBytes internal Flash version) embeds a total of 16 Kbytes high-speed SRAM (8 Kbytes SRAM0 and 8 Kbytes SRAM1).
The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32bit internal bus. Its 128-bit wide memory interface increases performance. The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
SAM3U Series operation. However, it is safer to connect it directly to GND for the final application. 9.1.3.6 Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 9.1.3.7 Unique Identifier Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the user.
9.1.4 Boot Strategies The system always boots at address 0x0. To ensure a maximum boot possibilities the memory layout can be changed via GPNVM. A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface. Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.
SAM3U Series – Error Report, including error flag, correctable error flag and word address being detected erroneous – Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages 10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... The System Controller User Interface also embeds the registers used to configure the Matrix.
Figure 10-1.
SAM3U Series 10.1 System Controller and Peripheral Mapping Please refer to Figure 8-1“SAM3U Memory Mapping” on page 30 . All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3U embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDBU • Brownout Detector on VDDCORE • Supply Monitor on VDDUTMI 10.2.1 Power-on-Reset on VDDBU The Power-on-Reset monitors VDDBU.
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the Slow Clock source. The Supply Controller starts up the device by enabling the Voltage Regulator, then it generates the proper reset signals to the core power supply. It also enables to set the system in different low power modes and to wake it up from a wide range of events. 10.
SAM3U Series 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system.
10.7 Watchdog Timer • 16-bit key-protected once-only Programmable Counter • Windowed, prevents the processor to be in a dead-lock on the watchdog access 10.8 SysTick Timer • 24-bit down counter • Self-reload capability • Flexible system timer 10.9 Real-time Timer • Real-time Timer, allowing backup of time with different accuracies – 32-bit Free-running back-up Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm Register capable to generate a wake-up of the system 10.
SAM3U Series 10.13 Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. SAM3U Chip IDs Register - Engineering Samples Chip Name Flash Size KByte Pin Count CHIPID_CIDR CHIPID_EXID SAM3U4C 256 100 0x28000960 0x0 SAM3U2C 128 100 0x280A0760 0x0 SAM3U1C 64 100 0x28090560 0x0 SAM3U4E 256 144 0x28100960 0x0 SAM3U2E 128 144 0x281A0760 0x0 SAM3U1E 64 144 0x28190560 0x0 • JTAG ID: 0x0582A03F Table 10-2.
11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM3U. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always clocked. Please refer to the table below. Table 11-1.
SAM3U Series 11.2 Peripheral Signal Multiplexing on I/O Lines The SAM3U features 3 PIO controllers, PIOA, PIOB and PIOC that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following pages define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.
11.2.1 PIO Controller A Multiplexing Table 11-2.
SAM3U Series 11.2.2 PIO Controller B Multiplexing Table 11-3.
11.2.3 PIO Controller C Multiplexing Table 11-4.
SAM3U Series 12. Embedded Peripherals Overview 12.
12.4 Universal Synchronous Asynchronous Receiver Transmitter (USART) • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.
SAM3U Series – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/Down Capabilities – Quadrature Decoder Logic • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 12.
12.8 High Speed Multimedia Card Interface (HSMCI) • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with SD Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V2.0. • Compatibility with CE-ATA Specification 1.
SAM3U Series 12.10 Analog-to-Digital Converter (ADC) Two ADCs are embedded in the product. 12.10.1 12-bit High Speed ADC • 8-channel ADC • 12-bit 1 Msamples/sec.
13. Package Drawings Figure 13-1.
SAM3U Series Figure 13-2.
Figure 13-3. 144-lead LQFP Package Drawing Notes: 1. This drawing is for general information only; refer to JEDEe Drawing MS-026 for additional information. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. b dimension by more than 0.08 mm.
SAM3U Series Figure 13-4. 144-ball TFBGA Package Drawing All dimensions are in mm.
14. Ordering Information Table 14-1.
SAM3U Series Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the review and approval loop. Doc. Rev 6430FS Comments Change Request Ref. Figure 14-1, “ATSAM3U4/2/1 Ordering Information”, updated with MRL B devices 8130 Replaced all mentions of 100-ball LFBGA into 100-ball TFBGA 8044 Section 9.1.3.1 ”Flash Overview”, corrected wrong flash size for SAM3U1- 256KBytes replaced by 64KBytes 8029 Doc.
Doc. Rev 6430CS Doc Rev 6430BS Change Request Ref. Comments Section 2. ”SAM3U Block Diagram”, changed orientation of block diagrams. Section 5. ”Power Considerations”, fixed grammar in Voltage ranges. Section 3. ”Signal Description”, USART signal DCD0 is an Input rfo Figure 5-1 ”Single Supply”, Main supply range is 1.8V-3.6V. Figure 5-1, Figure 5-2, Figure 5-3, updated “Note” below figures, “With Main Supply <2.0V USB and ADC are not usable. 6698 Section 5.
SAM3U Series Doc Rev 6430BS Change Request Ref. Comments (Continued) Section 6.6 ”NRSTB Pin”, VDDIO changed to VDDBU Section 6. ”Input/Output Lines”, replaces Section 5.8 “Programmable I/O Lines”. Section 6.1 ”General Purpose I/O Lines (GPIO)” and Section 6.2 ”System I/O Lines”, replace Section 6. “I/O Line Considerations”. Figure 6-1 ”On-Die Termination schematic”, added. Section 6.8 “PIO Controllers”, removed. Section 8. ”Product Mapping”, title changed from “Memories”. Section 9.
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