Datasheet

35
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
Figure 10-2. Clock Generator Block Diagram
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock, HCLK
• the Free running processor clock, FCLK
• the Cortex SysTick external clock
• the Master Clock, MCK, in particular to the Matrix and the memory interfaces
• the USB Clock, UDPCK
• independent peripheral clocks, typically at the frequency of MCK
• three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at
4 MHz.
The user can trim the 8 and 12 MHz RC Oscillator frequency by software.
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
ControlStatus
PLL and
Divider A
PLLA Clock
PLLACK
12M Main
Oscillator
PLL and
Divider B
On Chip
32k RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
XTALSEL
PLLB Clock
PLLBCK
On Chip
12/8/4 MHz
RC OSC
MAINSEL