Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 64 MHz I/O number 47

Features

• Core

– ARM

Cortex

-M3 revision 2.0 running at up to 64 MHz

– Memory Protection Unit (MPU)

– Thumb

-2 instruction set

• Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1

products

• Memories

– 512 Kbytes Single Plane (SAM3S8) embedded Flash, 128-bit wide access, memory

accelerator

– 512 Kbytes Dual Plane (SAM3SD8) embedded Flash, 128-bit wide access, memory

accelerator

– 64 Kbytes embedded SRAM

– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines

– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash

support

• System

– Embedded voltage regulator for single supply operation

– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation

– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure

Detection and optional low-power 32.768 kHz for RTC or device clock

– RTC with Gregorian and Persian Calendar mode, waveform generation in low-

power modes

– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default

frequency for device startup. In-application trimming access for frequency

adjustment

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– Two PLLs up to 130 MHz for device clock and for USB

– Temperature Sensor

– Up to 24 peripheral DMA (PDC) channels

• Low Power Modes

– Sleep and Backup modes, down to 1 µA in Backup mode

– Ultra low-power RTC

• Peripherals

– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip

Transceiver

– Up to 3 USARTs with ISO7816, IrDA

, RS-485, SPI, Manchester and Modem Mode

– Two 2-wire UARTs

– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller

(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)

– 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM

mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper

Motor

– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time

Generator Counter for Motor Control

– 32-bit Real-time Timer and RTC with calendar and alarm features

– Up to 15-channel, 1Msps ADC with differential input mode and programmable gain

stage and auto calibration

– One 2-channel 12-bit 1Msps DAC

– One Analog Comparator with flexible input selection, Selectable input hysteresis

– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)

• I/O

– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),

debouncing, glitch filtering and on-die Series Resistor Termination

– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel

Capture Mode

• Packages

– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA,9x9mm,pitch0.8mm

– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm

AT91SAM

ARM-based

Flash MCU

SAM3S8/SD8

Series

Summary

11090BS–ATARM–22-Oct-13

Summary of content (57 pages)

PAGE 1
Features • Core • • • • • • • – ARM® Cortex®-M3 revision 2.
PAGE 2
1. Description The Atmel SAM3S8/SD8 series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 64 MHz and features up to 512 Kbytes of Flash (dual plane on SAM3SD8) and up to 64 Kbytes of SRAM.
PAGE 3
SAM3S8/SD8 Summary 2. Block Diagram TST System Controller UT VD DO VD DI N JT AG SE L SAM3S8/SD8 100-pin version Block Diagram TD TDI TMO TC S/S K/ WD SW IO CL K Figure 2-1.
PAGE 4
TST System Controller DO VD DI N VD JT AG SE L UT SAM3S8/SD8 64-pin version Block Diagram TD TDI TMO TC S/S K/ W D SW IO CL K Figure 2-2.
PAGE 5
SAM3S8/SD8 Summary 3. Signal Description Table 3-1 gives details on signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power 1.8V to 3.6V(4) VDDOUT Voltage Regulator Output Power 1.
PAGE 6
Table 3-1.
PAGE 7
SAM3S8/SD8 Summary Table 3-1.
PAGE 8
Table 3-1.
PAGE 9
SAM3S8/SD8 Summary 4. Package and Pinout SAM3S8/SD8 devices are pin-to-pin compatible with AT91SAM7S legacy products for 64-pin version. Furthermore, SAM3S8/SD8 products have new functionalities referenced in italic in Table 4-1, Table 4-3. 4.1 4.1.1 SAM3S8C/8DC Package and Pinout 100-Lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball TFBGA Package Outline The 100-Ball TFBGA package has a 0.
PAGE 10
4.1.3 100-Lead LQFP Pinout Table 4-1.
PAGE 11
SAM3S8/SD8 Summary 4.1.4 100-Ball TFBGA Pinout Table 4-2.
PAGE 12
4.2 4.2.1 SAM3S8B/D8B Package and Pinout 64-Lead LQFP Package Outline Figure 4-3. Orientation of the 64-lead LQFP Package 33 48 49 32 64 17 16 1 4.2.2 64-lead QFN Package Outline Figure 4-4.
PAGE 13
SAM3S8/SD8 Summary 4.2.3 64-Lead LQFP and QFN Pinout Table 4-3.
PAGE 14
5. Power Considerations 5.1 Power Supplies The SAM3S8/SD8 has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V. • VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply. Voltage ranges from 1.8V to 3.6V.
PAGE 15
SAM3S8/SD8 Summary Figure 5-1. Single Supply VDDIO Main Supply (1.8V-3.6V) USB Transceivers. ADC, DAC Analog Comp. VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.0 V, USB and ADC/DAC and Analog comparator are not usable. With Main Supply ≥ 2.0V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. Figure 5-2. Core Externally Supplied VDDIO Main Supply (1.62V-3.6V) USB Transceivers.
PAGE 16
Figure 5-3. Backup Battery ADC, DAC, Analog Comparator Supply (2.0V-3.6V) Backup Battery VDDIO USB Transceivers. + ADC, DAC Analog Comp. VDDIN Main Supply IN OUT 3.3V LDO VDDOUT Voltage Regulator VDDCORE ON/OFF VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. 5.
PAGE 17
SAM3S8/SD8 Summary • Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. Current Consumption in Wait mode is typically 15 µA (total current consumption) if the internal voltage regulator is used or 8 µA if an external regulator is used. In this mode, the clocks of the core, peripherals and memories are stopped.
PAGE 18
5.5.4 Low Power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low-power modes. Table 5-1.
PAGE 19
SAM3S8/SD8 Summary 5.6 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4.
PAGE 20
5.7 Fast Startup The SAM3S8/SD8 allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast startup signal to the Power Management Controller.
PAGE 21
SAM3S8/SD8 Summary 6. Input/Output Lines The SAM3S8/SD8 has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers.
PAGE 22
Table 6-1. System I/O Configuration Pin List.
PAGE 23
SAM3S8/SD8 Summary 6.3 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S8/SD8 series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet. 6.
PAGE 24
7. Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single cycle 32-bit multiply. • Hardware divide. • Thumb and Debug states. • Handler and Thread modes. • Low latency ISR entry and exit. 7.
PAGE 25
SAM3S8/SD8 Summary 7.5 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 7-3. SAM3S8_SD8 Master to Slave Access Masters Slaves 7.
PAGE 26
Table 7-4. 7.7 Peripheral DMA Controller Instance name Channel T/R SSC Transmit HSMCI Transmit PIOA Receive TWI1 Receive TWI0 Receive UART1 Receive UART0 Receive USART1 Receive USART0 Receive ADC Receive SPI Receive SSC Receive HSMCI Receive Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset.
PAGE 27
SAM3S8/SD8 Summary 8. Product Mapping Figure 8-1.
PAGE 28
9. Memories 9.1 9.1.1 Embedded Memories Internal SRAM The SAM3S8 device (512-Kbytes, single bank flash) embeds a total of 64-Kbytes high-speed SRAM. The SAM3SD8 device (512-Kbytes, dual bank flash) embeds a total of 64-Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and 0x23FF FFFF. 9.1.
PAGE 29
SAM3S8/SD8 Summary 9.1.3.4 Flash Speed The user needs to set the number of wait states depending on the frequency used: For more details, refer to the “AC Characteristics” sub-section of the product “Electrical Characteristics”. 9.1.3.5 Lock Regions Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 9-1.
PAGE 30
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. 9.1.3.10 SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART and USB. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 9.1.3.
PAGE 31
SAM3S8/SD8 Summary 9.2 External Memories The SAM3S8/SD8 features one External Bus Interface to provide an interface to a wide range of external memories and to any parallel peripheral. 9.2.
PAGE 32
Figure 10-1.
PAGE 33
SAM3S8/SD8 Summary 10.1 System Controller and Peripherals Mapping Please refer to Section 8-1 “SAM3S8/SD8 Product Mapping” on page 27. All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S8/SD8 embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 10.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO.
PAGE 34
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the software-programmable brownout detector allows detection of either a battery discharge or main voltage loss. The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator.
PAGE 35
SAM3S8/SD8 Summary Figure 10-2. Clock Generator Block Diagram Clock Generator XTALSEL On Chip 32k RC OSC XIN32 XOUT32 XIN Slow Clock SLCK Slow Clock Oscillator 12M Main Oscillator Main Clock MAINCK XOUT On Chip 12/8/4 MHz RC OSC MAINSEL PLL and Divider B PLLB Clock PLLBCK PLL and Divider A PLLA Clock PLLACK Status Control Power Management Controller 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system.
PAGE 36
Figure 10-3. Power Management Controller Block Diagram Processor Clock Controller HCK int Sleep Mode Divider /8 SystTick FCLK Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..
PAGE 37
SAM3S8/SD8 Summary 10.9 Real-Time Timer • Real-Time Timer, allowing backup of time with different accuracies – 32-bit Free-running backup Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm Register capable to generate a wake-up of the system through the Shut Down Controller 10.10 Real Time Clock • Low power consumption • Full asynchronous design • Two hundred year Gregorian and Persian calendar • Programmable Periodic Interrupt • Trimmable 32.
PAGE 38
10.13 Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. SAM3S8/SD8 Hip IDs Register Chip Name Flash Size (KBytes) Pin Count CHIPID_CIDR CHIPID_EXID SAM3S8B (Rev A) 512 64 0x289B0A60 0x0 SAM3S8C (Rev A) 512 100 0x28AB0A60 0x0 SAM3SD8B (Rev A) 512 64 0x299B0A60 0x0 SAM3SD8C (Rev A) 512 100 0x29AB0A60 0x0 • JTAG ID: 0x05B2D03F 10.
PAGE 39
SAM3S8/SD8 Summary – Lock of the configuration by the connected peripheral • Synchronous output, provides set and clear of several I/O lines in a single write • Write Protect Registers • Programmable Schmitt trigger inputs • Parallel capture mode – Can be used to interface a CMOS digital image sensor, an ADC....
PAGE 40
Table 10-3.
PAGE 41
SAM3S8/SD8 Summary 10.17.1 PIO Controller A Multiplexing Table 10-4.
PAGE 42
10.17.2 PIO Controller B Multiplexing Table 10-5.
PAGE 43
SAM3S8/SD8 Summary 10.17.3 PIO Controller C Multiplexing Table 10-6.
PAGE 44
11. Embedded Peripherals Overview 11.
PAGE 45
SAM3S8/SD8 Summary 11.4 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.
PAGE 46
– Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels • Quadrature decoder – Advanced line filtering – Position / revolution / speed • 2-bit Gray Up/Down Counter for Stepper Motor 11.
PAGE 47
SAM3S8/SD8 Summary • One programmable Fault Input providing an asynchronous protection of outputs • Stepper motor control (2 Channels) 11.8 High Speed Multimedia Card Interface (HSMCI) • 4-bit or 1-bit Interface • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with SD and SDHC Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V1.1. • Compatibility with CE-ATA Specification 1.
PAGE 48
• Single ended/differential conversion • Programmable gain: 1, 2, 4 11.
PAGE 49
SAM3S8/SD8 Summary – Temperature Sensor – ADVREF – AD0 to AD3 ADC channels • Plus input selection: – All analog inputs • output selection: – Internal signal – external pin – selectable inverter • window function • Interrupt on: – Rising edge, Falling edge, toggle – Signal above/below window, signal inside/outside window 11.
PAGE 50
12. Package Drawings The SAM3S8/SD8 series devices are available in LQFP, QFN and TFBGA packages. Figure 12-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
PAGE 51
SAM3S8/SD8 Summary Figure 12-2.
PAGE 52
Figure 12-3. 64-lead LQFP Package Mechanical Drawing Table 12-1. Symbol 64-lead LQFP Package Dimensions (in mm) Millimeter Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC R2 0.08 R1 0.08 q 0° θ1 0° – 0.383 BSC 0.20 0.003 – 0.008 – – 0.003 – – 3.5° 7° 0° 3.
PAGE 53
SAM3S8/SD8 Summary Table 12-1. Symbol 64-lead LQFP Package Dimensions (in mm) (Continued) Millimeter Min Nom Inch Max Min Nom Max S 0.20 – – 0.008 – – b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 BSC. 0.020 BSC. D2 7.50 0.285 E2 7.50 0.285 aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.
PAGE 54
Figure 12-4.
PAGE 55
SAM3S8/SD8 Summary 13. Ordering Information Table 13-1.
PAGE 56
Revision History In the information that follows, the most recent version of the document is referenced first. Change Request Ref. Doc. Rev Comments 11090BS Corrected Figure 12-3 “64-lead LQFP Package Mechanical Drawing” and inserted Table 12-1 “64-lead LQFP Package Dimensions (in mm)”. Doc. Rev Comments 11090AS First issue 56 9389 Change Request Ref.
PAGE 57
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