Datasheet

40
6500AS–ATARM–11-Dec-09
SAM3S Summary
Figure 10-3. SAM3S Power Management Controller Block Diagram
The SysTick calibration value is fixed at 8000 which allows the generation of a time base of 1 ms
with SystTick clock at 8 MHz (max HCLK/8 = 64 MHz/8).
10.7 Watchdog Timer
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access.
10.8 SysTick Timer
• 24-bit down counter
• Self-reload capability
• Flexible System timer
10.9 Real Time Timer
• Real Time Timer, allowing backup of time with different accuracies
– 32-bit free-running back-up counter
– Integrates a 16-bit programmable prescaler running on slow clock
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
HCK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
PLLBCK
pck[..]
PLLBCK
PLLBCK
UDPCK
ON/OFF
ON/OFF
FCLK
SystTick
Divider
/8