Datasheet

6500AS–ATARM–11-Dec-09

SAM3S Summary

7.7 Debug and Test Features

• Debug access to all memory and registers in the system, including Cortex-M3 register bank

when the core is running, halted, or held in reset.

• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access

• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches

• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and

system profiling

• Instrumentation Trace Macrocell (ITM) for support of printf style debugging

• IEEE1149.1 JTAG Boundary-can on All Digital Pins

UART0 Receive x x

USART1 Receive x x

USART0 Receive x x

ADC Receive x x

SPI Receive x x

SSC Receive x x

HSMCI Receive x N/A

PIOA Receive x x

Table 7-4. Peripheral DMA Controller (Continued)

Instance Name Channel T/R 100 & 64 Pins 48 Pins