Datasheet

28
6500AS–ATARM–11-Dec-09
SAM3S Summary
7.5 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired and shown as “-” in the following table.
7.6 Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-3. SAM3S Master to Slave Access
Masters 0 1 2 3
Slaves
Cortex-M3 I/D
Bus
Cortex-M3 S
Bus
PDC CRCCU
0 Internal SRAM - X X X
1 Internal ROM X - X X
2 Internal Flash X - - X
3 External Bus Interface - X X X
4 Peripheral Bridge - X X -
Table 7-4. Peripheral DMA Controller
Instance Name Channel T/R 100 & 64 Pins 48 Pins
PWM Transmit x x
TWI1 Transmit x x
TWI0 Transmit x x
UART1 Transmit x x
UART0 Transmit x x
USART1 Transmit x N/A
USART0 Transmit x x
DAC Transmit x N/A
SPI Transmit x x
SSC Transmit x x
HSMCI Transmit x N/A
PIOA Transmit x x
TWI1 Receive x x
TWI0 Receive x x
UART1 Receive x N/A