Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesARM Processor Microcontroller QFP 64

NOTE: This is a summary document.

The complete document is available on

the Atmel website at www.atmel.com.

Features

• Core

– ARM

Cortex

-M3 revision 2.0 running at up to 64 MHz

– Memory Protection Unit (MPU)

–Thumb

-2 instruction set

• Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions)

• Memories

– From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

single plane

– From 16 to 48 Kbytes embedded SRAM

– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines

– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash

support

– Memory Protection Unit (MPU)

• System

– Embedded voltage regulator for single supply operation

– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe

operation

– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure

Detection and optional low power 32.768 kHz for RTC or device clock

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default

frequency for device startup. In-application trimming access for frequency

adjustment

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– Two PLLs up to 130 MHz for device clock and for USB

– Temperature Sensor

– Up to 22 peripheral DMA (PDC) channels

• Low Power Modes

– Sleep and Backup modes, down to 3 µA in Backup mode

– Ultra low power RTC

• Peripherals

– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip

Transceiver

– Up to 2 USARTs with ISO7816, IrDA

, RS-485, SPI, Manchester and Modem Mode

– Two 2-wire UARTs

– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller

(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)

– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and

PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for

Stepper Motor

– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time

Generator Counter for Motor Control

– 32-bit Real-time Timer and RTC with calendar and alarm features

– Up to 15-channel, 1Msps ADC with differential input mode and programmable gain

stage

– One 2-channel 12-bit 1Msps DAC

– One Analog Comparator with flexible input selection, window mode, Selectable

input hysteresis

– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)

• I/O

– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),

debouncing, glitch filtering and on-die Series Resistor Termination

– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel

Capture Mode

• Packages

– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm / 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm

– 64-lead LQFP, 12 x 12 mm, pitch 0.5 mm / 64-pad QFN 9x9 mm, pitch 0.45 mm

– 48-lead LQFP, 9 x 9 mm, pitch 0.5 mm / 48-pad QFN 7x7 mm, pitch 0.45 mm

AT91 ARM

Cortex M3-based

Processor

ATSAM3S Series

Preliminary

Summary

6500AS–ATARM–11-Dec-09

Summary of content (65 pages)

PAGE 1
Features • Core • • • • • • • – ARM® Cortex®-M3 revision 2.
PAGE 2
1. SAM3S Description Atmel's SAM3S series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48 Kbytes of SRAM.
PAGE 3
SAM3S Summary 2. SAM3S Block Diagram TST System Controller UT O VD D JTA G VD D IN SE L SAM3S 100-pin Version Block Diagram TD TDI TMO TC S/S K/ W SW DI CL O K Figure 2-1. Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M In-Circuit Emulator 24-Bit N Cortex-M3 Processor SysTick Counter V Fmax 64 MHz I C 3-20 MHz Osc.
PAGE 4
System Controller O UT VD D IN VD D JT AG TD TST SE L SAM3S 64-pin Version Block Diagram I TD O TM S/ TC SW K/ DIO SW CL K Figure 2-2. Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M In-Circuit Emulator 3-20 MHz Osc.
PAGE 5
SAM3S Summary O UT IN System Controller VD D VD D TD TST JT AG SE L SAM3S 48-pin Version Block Diagram I TD O TM S/ TC SW K/ DIO SW CL K Figure 2-3. Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M XIN XOUT Flash Unique Identifier In-Circuit Emulator 3-20 MHz Osc.
PAGE 6
3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power 1.8V to 3.6V(4) VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.
PAGE 7
SAM3S Summary Table 3-1.
PAGE 8
Table 3-1.
PAGE 9
SAM3S Summary Table 3-1.
PAGE 10
4. Package and Pinout 4.1 SAM3S4/2/1C Package and Pinout Figure 4-2 shows the orientation of the 100-ball LFBGA Package The 100-ball LFBGA pinout will be specified as soon as the first layout of the device is completed. 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball LFBGA Package Outline The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm. Figure 4-2.
PAGE 11
SAM3S Summary 4.1.3 Table 4-1.
PAGE 12
4.1.4 100-ball LFBGA Pinout Table 4-2.
PAGE 13
SAM3S Summary 4.2 SAM3S4/2/1B Package and Pinout Figure 4-3. Orientation of the 64-pad QFN Package 64 49 1 48 16 33 32 17 Figure 4-4.
PAGE 14
4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. Table 4-3.
PAGE 15
SAM3S Summary 4.3 SAM3S4/2/1A Package and Pinout Figure 4-5. Orientation of the 48-pad QFN Package 48 37 1 36 12 25 13 24 TOP VIEW Figure 4-6.
PAGE 16
4.3.1 48-Lead LQFP and QFN Pinout Table 4-4.
PAGE 17
SAM3S Summary 5. Power Considerations 5.1 Power Supplies The SAM3S product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V and 1.95V. • VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers); USB transceiver; Backup part, 32kHz crystal oscillator and oscillator pads; ranges from 1.62V and 3.6V • VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply; Voltage ranges from 1.
PAGE 18
Figure 5-1. Single Supply VDDIO Main Supply (1.8V-3.6V) USB Transceivers. ADC, DAC Analog Comp. VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.4 V, USB and ADC/DAC and Analog comparator are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. Figure 5-2. Core Externally Supplied VDDIO Main Supply (1.62V-3.6V) USB Transceivers. Can be the same supply ADC, DAC, Analog Comparator Supply (2.4V-3.
PAGE 19
SAM3S Summary Figure 5-3. Backup Battery ADC, DAC, Analog Comparator Supply (2.4V-3.6V) Backup Battery VDDIO USB Transceivers. + ADC, DAC Analog Comp. VDDIN Main Supply IN OUT 3.3V LDO VDDOUT Voltage Regulator VDDCORE ON/OFF VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. 5.
PAGE 20
• WKUPEN0-15 pins (level transition, configurable debouncing) • Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. Current Consumption in Wait mode is typically 15 µA (total current consumption) if the internal voltage regulator is used or 8 µA if an external regulator is used.
PAGE 21
SAM3S Summary 5.5.4 Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Table 5-1.
PAGE 22
5.6 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4.
PAGE 23
SAM3S Summary 5.7 Fast Startup The SAM3S allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast startup signal to the Power Management Controller.
PAGE 24
6. Input/Output Lines The SAM3S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers.
PAGE 25
SAM3S Summary Table 6-1. System I/O Configuration Pin List.
PAGE 26
6.3 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet. 6.4 NRST Pin The NRST pin is bidirectional.
PAGE 27
SAM3S Summary 7. Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit • Harvard processor architecture enabling simultaneous instruction fetch with data load/store • Three-stage pipeline • Single cycle 32-bit multiply • Hardware divide • Thumb and Debug states • Handler and Thread modes • Low latency ISR entry and exit 7.
PAGE 28
7.5 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired and shown as “-” in the following table. Table 7-3. SAM3S Master to Slave Access Masters Slaves 7.
PAGE 29
SAM3S Summary Table 7-4. 7.7 Peripheral DMA Controller (Continued) Instance Name Channel T/R 100 & 64 Pins 48 Pins UART0 Receive x x USART1 Receive x x USART0 Receive x x ADC Receive x x SPI Receive x x SSC Receive x x HSMCI Receive x N/A PIOA Receive x x Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset.
PAGE 30
8. Product Mapping Figure 8-1.
PAGE 31
SAM3S Summary 9. Memories 9.1 9.1.1 Embedded Memories Internal SRAM The ATSAM3S4 product (256-Kbyte internal Flash version) embeds a total of 48 Kbytes highspeed SRAM. The ATSAM3S2 product (128-Kbyte internal Flash version) embeds a total of 32 Kbytes highspeed SRAM. The ATSAM3S1 product (64-Kbyte internal Flash version) embeds a total of 16 Kbytes highspeed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region.
PAGE 32
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 9.1.3.4 Flash Speed The user needs to set the number of wait states depending on the frequency used. For more details, refer to the AC Characteristics sub section in the product Electrical Characteristics Section. 9.1.3.5 Lock Regions Several lock bits used to protect write and erase operations on lock regions.
PAGE 33
SAM3S Summary 9.1.3.9 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
PAGE 34
– Chip Select, Write enable or Read enable Control Mode – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported • Additional Logic for NAND Flash 34 SAM3S Summary 6500AS–ATARM–11-Dec-09
PAGE 35
SAM3S Summary 10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc...
PAGE 36
Figure 10-1.
PAGE 37
SAM3S Summary 10.1 System Controller and Peripherals Mapping Please refer to Section 8-1 “SAM3S Product Mapping” on page 30. All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 10.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO.
PAGE 38
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the software-programmable brownout detector allows detection of either a battery discharge or main voltage loss. The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator.
PAGE 39
SAM3S Summary Figure 10-2. Clock Generator Block Diagram Clock Generator XTALSEL On Chip 32 kHz RC OSC Slow Clock SLCK XIN32 XOUT32 XIN XOUT Slow Clock Oscillator 3-20 MHz Main Oscillator Main Clock MAINCK On Chip 12/8/4 MHz RC OSC MAINSEL PLL and Divider B PLLB Clock PLLBCK PLL and Divider A PLLA Clock PLLACK Status Control Power Management Controller 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system.
PAGE 40
Figure 10-3. SAM3S Power Management Controller Block Diagram Processor Clock Controller HCK int Sleep Mode Divider /8 SystTick FCLK Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..
PAGE 41
SAM3S Summary – Alarm register capable to generate a wake-up of the system through the Shut Down Controller 10.10 Real Time Clock • Low power consumption • Full asynchronous design • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 10.11 General Purpose Backup Registers • Eight 32-bit general-purpose backup registers 10.
PAGE 42
10.14 UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter 10.
PAGE 43
SAM3S Summary 11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM3S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 11-1.
PAGE 44
11.2 Peripheral Signal Multiplexing on I/O Lines The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB) or 3 PIO controllers on the 100-pin version, (PIOA, PIOB, PIOC), that multiplex the I/O lines of the peripheral set. The SAM3S 64-pin and 100-pin PIO Controllers control up to 32 lines. (See, Table 10-2.) Each line can be assigned to one of three peripheral functions: A, B or C.
PAGE 45
SAM3S Summary 11.2.1 PIO Controller A Multiplexing Table 11-2.
PAGE 46
11.2.2 PIO Controller B Multiplexing Table 11-3.
PAGE 47
SAM3S Summary 11.2.3 PIO Controller C Multiplexing Table 11-4.
PAGE 48
12. Embedded Peripherals Overview 12.
PAGE 49
SAM3S Summary 12.4 Universal Synchronous Asynchronous Receiver Transceiver (USART) • Programmable Baud Rate Generator with Fractional Baud rate support • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.
PAGE 50
– Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels • Quadrature decoder – Advanced line filtering – Position / revolution / speed • 2-bit Gray Up/Down Counter for Stepper Motor 12.
PAGE 51
SAM3S Summary • Programmable Fault Input providing an asynchronous protection of outputs • Stepper motor control (2 Channels) 12.8 High Speed Multimedia Card Interface (HSMCI) • 4-bit or 1-bit Interface • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with SD and SDHC Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V1.1. • Compatibility with CE-ATA Specification 1.
PAGE 52
• Programmable gain: 1, 2, 4 12.11 Digital-to-Analog Converter (DAC) • Up to 2 channel 12-bit DAC • Up to 2 mega-samples conversion rate in single channel mode • Flexible conversion range • Multiple trigger sources for each channel • 2 Sample/Hold (S/H) outputs • Built-in offset and gain calibration • Possibility to drive output to ground • Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H stage) • Two PDC channels • Power reduction mode 12.
PAGE 53
SAM3S Summary • output selection: – Internal signal – external pin – selectable inverter • window function • Interrupt on: – Rising edge, Falling edge, toggle – Signal above/below window, signal inside/outside window 12.
PAGE 54
13. Package Drawings The SAM3S series devices are available in LQFP, QFN and LFBGA packages. Figure 13-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
PAGE 55
SAM3S Summary Figure 13-2.
PAGE 56
Figure 13-3.
PAGE 57
SAM3S Summary Table 13-1. 48-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.
PAGE 58
Table 13-2. 64-lead LQFP Package Dimensions (in mm) Symbol Millimeter Inch Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
PAGE 59
SAM3S Summary Figure 13-4.
PAGE 60
Table 13-3. 48-pad QFN Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.050 – – 0.002 A2 – 0.65 0.70 – 0.026 0.028 A3 b 0.20 REF 0.18 D D2 0.20 0.008 REF 0.23 0.007 7.00 bsc 5.45 E 5.60 0.008 0.009 0.276 bsc 5.75 0.215 7.00 bsc 0.220 0.226 0.276 bsc E2 5.45 5.60 5.75 0.215 0.220 0.226 L 0.35 0.40 0.45 0.014 0.016 0.018 e R 0.50 bsc 0.09 – 0.020 bsc – 0.
PAGE 61
SAM3S Summary Figure 13-5.
PAGE 62
14. Ordering Information Table 14-1.
PAGE 63
SAM3S Summary Revision History Doc. Rev Comments 6500AS First issue Change Request Ref.
PAGE 64
SAM3S Summary 6500AS–ATARM–11-Dec-09
PAGE 65
Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.