Datasheet

SAM3S [SUMMARY]

6500ES–ATARM–11-Feb-13

z Eight endpoints

z Endpoint 0: 64 bytes

z Endpoint 1 and 2: 64 bytes ping-pong

z Endpoint 3: 64 bytes

z Endpoint 4 and 5: 512 bytes ping-pong

z Endpoint 6 and 7: 64 bytes ping-pong

z Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints

z Suspend/resume logic

z Integrated Pull-up on DDP

z Pull-down resistor on DDM and DDP when disabled

12.10 Analog-to-Digital Converter (ADC)

z up to 16 Channels,

z 10/12-bit resolution

z up to 1 MSample/s

z programmable sequence of conversion on each channel

z Integrated temperature sensor

z Single ended/differential conversion

z Programmable gain: 1, 2, 4

12.11 Digital-to-Analog Converter (DAC)

z Up to 2 channel 12-bit DAC

z Up to 2 mega-samples conversion rate in single channel mode

z Flexible conversion range

z Multiple trigger sources for each channel

z 2 Sample/Hold (S/H) outputs

z Built-in offset and gain calibration

z Possibility to drive output to ground

z Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H stage)

z Two PDC channels

z Power reduction mode

12.12 Static Memory Controller

z 16-Mbyte Address Space per Chip Select

z 8- bit Data Bus

z Word, Halfword, Byte Transfers

z Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

z Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

z Programmable Data Float Time per Chip Select

z External Wait Request

z Automatic Switch to Slow Clock Mode

z Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

z NAND FLASH additional logic supporting NAND Flash with Multiplexed Data/Address buses

z Hardware Configurable number of chip select from 1 to 4

z Programmable timing on a per chip select basis