Datasheet

SAM3S [SUMMARY]

6500ES–ATARM–11-Feb-13

12. Embedded Peripherals Overview

12.1 Serial Peripheral Interface (SPI)

z Supports communication with serial external devices

z Four chip selects with external decoder support allow communication with up to 15 peripherals

z Serial memories, such as DataFlash and 3-wire EEPROMs

z Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors

z External co-processors

z Master or slave serial peripheral bus interface

z 8- to 16-bit programmable data length per chip select

z Programmable phase and polarity per chip select

z Programmable transfer delays between consecutive transfers and between clock and data per chip select

z Programmable delay between consecutive transfers

z Selectable mode fault detection

z Very fast transfers supported

z Transfers with baud rates up to MCK

z The chip select line may be left active to speed up transfers on the same device

12.2 Two Wire Interface (TWI)

z Master, Multi-Master and Slave Mode Operation

z Compatibility with Atmel two-wire interface, serial memory and I

C compatible devices

z One, two or three bytes for slave address

z Sequential read/write operations

z Bit Rate: Up to 400 kbit/s

z General Call Supported in Slave Mode

z Connecting to PDC channel capabilities optimizes data transfers in Master Mode only

z One channel for the receiver, one channel for the transmitter

z Next buffer support

12.3 Universal Asynchronous Receiver Transceiver (UART)

z Two-pin UART

z Independent receiver and transmitter with a common programmable Baud Rate Generator

z Even, Odd, Mark or Space Parity Generation

z Parity, Framing and Overrun Error Detection

z Automatic Echo, Local Loopback and Remote Loopback Channel Modes

z Support for two PDC channels with connection to receiver and transmitter

12.4 Universal Synchronous Asynchronous Receiver Transceiver (USART)

z Programmable Baud Rate Generator with Fractional Baud rate support

z 5- to 9-bit full-duplex synchronous or asynchronous serial communications

z 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode

z Parity generation and error detection

z Framing error detection, overrun error detection

z MSB- or LSB-first

z Optional break generation and detection