Datasheet

36
SAM3S [SUMMARY]
6500ES–ATARM–11-Feb-13
The Supply Controller starts up the device by sequentially enabling the internal power switches and the Voltage
Regulator, then it generates the proper reset signals to the core power supply.
It also enables to set the system in different low power modes and to wake it up from a wide range of events.
10.5 Clock Generator
The Clock Generator is made up of:
z One Low Power 32768Hz Slow Clock oscillator with bypass mode
z One Low-Power RC oscillator
z One 3-20 MHz Crystal Oscillator, which can be bypassed
z One Fast RC oscillator factory programmed, 3 output frequencies can be selected: 4, 8 or 12 MHz. By default 4
MHz is selected.
z One 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller
z One 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and to the
peripherals. The PLLA input frequency is from 3.5 to 20 MHz.
Figure 10-2. Clock Generator Block Diagram
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
z the Processor Clock, HCLK
z the Free running processor clock, FCLK
z the Cortex SysTick external clock
z the Master Clock, MCK, in particular to the Matrix and the memory interfaces
z the USB Clock, UDPCK
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
ControlStatus
PLL and
Divider A
PLLA Clock
PLLACK
3-20 MHz
Main
Oscillator
PLL and
Divider B
On Chip
32 kHz
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
XTALSEL
PLLB Clock
PLLBCK
On Chip
12/8/4 MHz
RC OSC
MAINSEL