Datasheet

33
SAM3S [SUMMARY]
6500ES–ATARM–11-Feb-13
9.1.3.11 GPNVM Bits
The SAM3S features two GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit”
and “Set GPNVM Bit” of the EEFC User Interface.
9.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via
GPNVM.
A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set
General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears
the GPNVM Bit 1 and thus selects the boot from the ROM by default.
9.2 External Memories
The SAM3S features an External Bus Interface to provide the interface to a wide range of external memories and to any
parallel peripheral.
9.2.1 Static Memory Controller
z 8-bit Data Bus
z Up to 24-bit Address Bus (up to 16 MBytes linear per chip select)
z Up to 4 chip selects, Configurable Assignment
z Multiple Access Modes supported
z Chip Select, Write enable or Read enable Control Mode
z Asynchronous read in Page Mode supported (4- up to 32-byte page size)
z Multiple device adaptability
z Control signals programmable setup, pulse and hold time for each Memory Bank
z Multiple Wait State Management
z Programmable Wait State Generation
z External Wait Request
z Programmable Data Float Time
z Slow Clock mode supported
z Additional Logic for NAND Flash
Table 9-2. General Purpose Non-volatile Memory Bits
GPNVMBit[#] Function
0 Security bit
1 Boot mode selection