Datasheet

SAM3S [SUMMARY]

6500ES–ATARM–11-Feb-13

7.7 Debug and Test Features

z Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is

running, halted, or held in reset.

z Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access

z Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches

z Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling

z Instrumentation Trace Macrocell (ITM) for support of printf style debugging

z IEEE1149.1 JTAG Boundary-can on All Digital Pins

USART1 Receive xx

USART0 Receive xx

ADC Receive xx

SPI Receive xx

SSC Receive xx

HSMCI Receive x N/A

PIOA Receive x x

Table 7-4. Peripheral DMA Controller (Continued)

Instance Name Channel T/R 100 & 64 Pins 48 Pins