Datasheet

27
SAM3S [SUMMARY]
6500ES–ATARM–11-Feb-13
7. Processor and Architecture
7.1 ARM Cortex-M3 Processor
z Version 2.0
z Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
z Harvard processor architecture enabling simultaneous instruction fetch with data load/store
z Three-stage pipeline
z Single cycle 32-bit multiply
z Hardware divide
z Thumb and Debug states
z Handler and Thread modes
z Low latency ISR entry and exit
7.2 APB/AHB bridge
The SAM3S product embeds one peripheral bridge:
The peripherals of the bridge are clocked by MCK.
7.3 Matrix Masters
The Bus Matrix of the SAM3S product manages 4 masters, which means that each master can perform an access
concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the
masters have the same decodings.
7.4 Matrix Slaves
The Bus Matrix of the SAM3S product manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration
per slave.
Table 7-1. List of Bus Matrix Masters
Master 0 Cortex-M3 Instruction/Data
Master 1 Cortex-M3 System
Master 2 Peripheral DMA Controller (PDC)
Master 3 CRC Calculation Unit
Table 7-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 Internal Flash
Slave 3 External Bus Interface
Slave 4 Peripheral Bridge