Datasheet

2
SAM3S [SUMMARY]
6500ES–ATARM–11-Feb-13
1. Features
• Core
– ARM
®
Cortex
®
-M3 revision 2.0 running at up to 64 MHz
– Memory Protection Unit (MPU)
– Thumb
®
-2 instruction set
• Pin-to-pin compatible with AT91SAM7S series (48- and 64-pin versions)
• Memories
–From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane
–From 16 to 48 Kbytes embedded SRAM
–16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support
– Memory Protection Unit (MPU)
• System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power 32.768
kHz for RTC or device clock
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-
application trimming access for frequency adjustment
–
Slow Clock Internal RC oscillator as permanent low-power mode device clock
–Two PLLs up to 130 MHz for device clock and for USB
– Temperature Sensor
–Up to 22 peripheral DMA (PDC) channels
• Low Power Modes
– Sleep and Backup modes, down to 1.8 µA in Backup mode
– Ultra low power RTC
• Peripherals
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip Transceiver
–Up to 2 USARTs with ISO7816, IrDA
®
, RS-485, SPI, Manchester and Modem Mode
–Two 2-wire UARTs
–Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller (I2S), 1 High Speed Multimedia Card
Interface (SDIO/SD Card/MMC)
–Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM mode. Quadrature Decoder
Logic and 2-bit Gray Up/Down Counter for Stepper Motor
–
4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control
– 32-bit Real-time Timer and RTC with calendar and alarm features
–Up to 15-channel, 1Msps ADC with differential input mode and programmable gain stage
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
–
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Write Protected Registers
• I/O
–Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die
Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel Capture Mode
• Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm