Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 64 MHz I/O number 79

This is a summary document.

The complete document is

available on the Atmel website

at www.atmel.com.

6500ES–ATARM–11-Feb-13

Description

Atmel's SAM3S series is a member of a family of 32-bit Flash microcontrollers based on the high performance ARM

Cortex-M3 processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48

Kbytes of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver, a High Speed MCI

for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Controller providing connection to SRAM,

PSRAM, NOR Flash, LCD Module and NAND Flash, 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM

timer, 6x general-purpose 16-bit timers, an RTC, an ADC, a 12-bit DAC and an analog comparator.

The SAM3S series is ready for capacitive touch thanks to the QTouch library, offering an easy way to implement buttons,

wheels and sliders

The SAM3S device is a medium range general purpose microcontroller with the best ratio in terms of reduced power

consumption, processing power and peripheral set. This enables the SAM3S to sustain a wide range of applications

including consumer, industrial control, and PC peripherals.

It operates from 1.62V to 3.6V and is available in 48-, 64- and 100-pin QFP, 48- and 64-pin QFN, and 100-pin BGA

packages.

The SAM3S series is the ideal migration path from the SAM7S series for applications that require more performance. The

SAM3S series is pin-to-pin compatible with the SAM7S series.

AT91SAM ARM-based Flash MCU

SAM3S

SUMMARY

Summary of content (60 pages)

PAGE 1
AT91SAM ARM-based Flash MCU SAM3S SUMMARY Description Atmel's SAM3S series is a member of a family of 32-bit Flash microcontrollers based on the high performance ARM Cortex-M3 processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48 Kbytes of SRAM.
PAGE 2
1. Features • Core • • • • • • • – ARM® Cortex®-M3 revision 2.
PAGE 3
1.1 Configuration Summary The SAM3S microcontrollers differ in memory size, package and features list. Table 1-1 below summarizes the configurations of the device family Table 1-1. Device Configuration Summary Flash SRAM Timer Counter Channels GPIOs UART/ USARTs ADC 12-bit DAC Output External Bus Interface HSMCI Package 1 port 4 bits LQFP100 BGA100 SAM3S4C 256 Kbytes single plane 48 Kbytes 6 79 2/2(1) 15 ch.
PAGE 4
2. SAM3S Block Diagram TST System Controller VD DO UT VD DI N JTA G SE L TD TDI TMO TC S/S K/ W SW DI CL O K Figure 2-1. SAM3S 100-pin Version Block Diagram Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M In-Circuit Emulator 24-Bit N Cortex-M3 Processor SysTick Counter V Fmax 64 MHz I C 3-20 MHz Osc.
PAGE 5
TST System Controller VD DO UT VD DI N JT AG SE L TD I TD O TM S/ TC SW K/ DIO SW CL K Figure 2-2. SAM3S 64-pin Version Block Diagram Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M In-Circuit Emulator 3-20 MHz Osc.
PAGE 6
TST System Controller VD DO UT VD DI N JT AG SE L TD I TD O TM S/ TC SW K/ DIO SW CL K Figure 2-3. SAM3S 48-pin Version Block Diagram Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M XIN XOUT Flash Unique Identifier In-Circuit Emulator 3-20 MHz Osc.
PAGE 7
3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power 1.8V to 3.6V(4) VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.
PAGE 8
Table 3-1.
PAGE 9
Table 3-1.
PAGE 10
Table 3-1.
PAGE 11
4. Package and Pinout 4.1 SAM3S4/2/1C Package and Pinout Figure 4-2 shows the orientation of the 100-ball TFBGA Package 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball TFBGA Package Outline The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm. Figure 4-2.
PAGE 12
4.1.3 100-Lead LQFP Pinout Table 4-1.
PAGE 13
4.1.4 100-ball TFBGA Pinout Table 4-2.
PAGE 14
4.2 SAM3S4/2/1B Package and Pinout Figure 4-3. Orientation of the 64-pad QFN Package 64 49 1 48 16 33 32 17 TOP VIEW Figure 4-4.
PAGE 15
4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. Table 4-3.
PAGE 16
4.3 SAM3S4/2/1A Package and Pinout Figure 4-5. Orientation of the 48-pad QFN Package 48 37 1 36 12 25 13 24 TOP VIEW Figure 4-6.
PAGE 17
4.3.1 48-Lead LQFP and QFN Pinout Table 4-4.
PAGE 18
5. Power Considerations 5.1 Power Supplies The SAM3S product has several types of power supply pins: 5.2 z VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V and 1.95V. z VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers); USB transceiver; Backup part, 32kHz crystal oscillator and oscillator pads; ranges from 1.62V and 3.6V z VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply; Voltage ranges from 1.
PAGE 19
Figure 5-2. Core Externally Supplied VDDIO Main Supply (1.62V-3.6V) USB Transceivers. Can be the same supply ADC, DAC Analog Comp. VDDIN ADC, DAC, Analog Comparator Supply (2.0V-3.6V) VDDOUT Voltage Regulator VDDCORE VDDCORE Supply (1.62V-1.95V) VDDPLL Note: For USB, VDDIO needs to be greater than 3.0V. For ADC, VDDIN needs to be greater than 2.0V For DAC, VDDIN needs to be greater than 2.4V. Figure 5-3 below provides an example of the powering scheme when using a backup battery.
PAGE 20
5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 Low Power Modes The various low power modes of the SAM3S are described below: 5.5.
PAGE 21
5.5.3 Sleep Mode The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application dependent. This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM = 0 in PMC_FSMR.
PAGE 22
5.6 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4.
PAGE 23
5.7 Fast Startup The device allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-up signal to the Power Management Controller.
PAGE 24
6. Input/Output Lines The SAM3S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers.
PAGE 25
Table 6-1. System I/O Configuration List SYSTEM_IO bit number Default function after reset Other function 12 ERASE PB12 Low Level at startup(1) 10 DDM PB10 - In Matrix User Interface Registers 11 DDP PB11 - 7 TCK/SWCLK PB7 - 6 TMS/SWDIO PB6 - (Refer to the SystemIO Configuration Register in the Bus Matrix section of the product datasheet.
PAGE 26
6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length.
PAGE 27
7. Processor and Architecture 7.1 ARM Cortex-M3 Processor 7.2 z Version 2.
PAGE 28
7.5 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired and shown as “-” in the following table. Table 7-3. SAM3S Master to Slave Access Masters Slaves 7.
PAGE 29
Table 7-4. 7.7 Peripheral DMA Controller (Continued) Instance Name Channel T/R 100 & 64 Pins 48 Pins USART1 Receive x x USART0 Receive x x ADC Receive x x SPI Receive x x SSC Receive x x HSMCI Receive x N/A PIOA Receive x x Debug and Test Features z Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset.
PAGE 30
8. Product Mapping Figure 8-1.
PAGE 31
9. Memories 9.1 Embedded Memories 9.1.1 Internal SRAM The ATSAM3S4 product (256-Kbyte internal Flash version) embeds a total of 48 Kbytes high-speed SRAM. The ATSAM3S2 product (128-Kbyte internal Flash version) embeds a total of 32 Kbytes high-speed SRAM. The ATSAM3S1 product (64-Kbyte internal Flash version) embeds a total of 16 Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region.
PAGE 32
9.1.3.5 Lock Regions Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 9-1. Number of Lock Bits Product Number of Lock Bits Lock Region Size ATSAM3S4 16 16 kbytes (64 pages) ATSAM3S2 8 16 kbytes (64 pages) ATSAM3S1 4 16 kbytes (64 pages) If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt.
PAGE 33
9.1.3.11 GPNVM Bits The SAM3S features two GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Table 9-2. General Purpose Non-volatile Memory Bits GPNVMBit[#] 9.1.4 Function 0 Security bit 1 Boot mode selection Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via GPNVM.
PAGE 34
10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... See the system controller block diagram in Figure 10-1 on page 34. Figure 10-1.
PAGE 35
10.1 System Controller and Peripheral Mapping Please refer to Section 8-1 “SAM3S Product Mapping” on page 30. All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 10.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO.
PAGE 36
The Supply Controller starts up the device by sequentially enabling the internal power switches and the Voltage Regulator, then it generates the proper reset signals to the core power supply. It also enables to set the system in different low power modes and to wake it up from a wide range of events. 10.
PAGE 37
z independent peripheral clocks, typically at the frequency of MCK z three programmable clock outputs: PCK0, PCK1 and PCK2 The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz. The user can trim the 8 and 12 MHz RC Oscillator frequency by software. Figure 10-3.
PAGE 38
10.9 Real Time Timer z Real Time Timer, allowing backup of time with different accuracies z 32-bit free-running back-up counter z Integrates a 16-bit programmable prescaler running on slow clock z Alarm register capable to generate a wake-up of the system through the Shut Down Controller 10.
PAGE 39
10.14 UART z Two-pin UART z Implemented features are 100% compatible with the standard Atmel USART z Independent receiver and transmitter with a common programmable Baud Rate Generator z Even, Odd, Mark or Space Parity Generation z Parity, Framing and Overrun Error Detection z Automatic Echo, Local Loopback and Remote Loopback Channel Modes z Support for two PDC channels with connection to receiver and transmitter 10.
PAGE 40
11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM3S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 11-1.
PAGE 41
11.2 Peripheral Signal Multiplexing on I/O Lines The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB) or 3 PIO controllers on the 100-pin version, (PIOA, PIOB, PIOC), that multiplex the I/O lines of the peripheral set. The SAM3S 64-pin and 100-pin PIO Controllers control up to 32 lines. (See, Table 10-2.) Each line can be assigned to one of three peripheral functions: A, B or C.
PAGE 42
11.2.1 PIO Controller A Multiplexing Table 11-2.
PAGE 43
11.2.2 PIO Controller B Multiplexing Table 11-3.
PAGE 44
11.2.3 PIO Controller C Multiplexing Table 11-4.
PAGE 45
12. Embedded Peripherals Overview 12.1 Serial Peripheral Interface (SPI) z z z 12.2 12.
PAGE 46
z By 8 or by-16 over-sampling receiver frequency z Hardware handshaking RTS-CTS z Receiver time-out and transmitter timeguard z Optional Multi-drop Mode with address generation and detection z Optional Manchester Encoding z Full modem line support on USART1 (DCD-DSR-DTR-RI) z RS485 with driver control signal z ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards z z SPI Mode z Master or Slave z Serial Clock programmable Phase and Polarity z SPI Serial Clock (SCK) Frequenc
PAGE 47
12.
PAGE 48
z Eight endpoints z Endpoint 0: 64 bytes z Endpoint 1 and 2: 64 bytes ping-pong z Endpoint 3: 64 bytes z Endpoint 4 and 5: 512 bytes ping-pong z Endpoint 6 and 7: 64 bytes ping-pong z Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints z Suspend/resume logic z Integrated Pull-up on DDP z Pull-down resistor on DDM and DDP when disabled 12.
PAGE 49
12.13 Analog Comparator z One analog comparator z High speed option vs. low power option z Selectable input hysteresis: z z 0, 20 mV, 50 mV Minus input selection: z DAC outputs z Temperature Sensor z ADVREF z AD0 to AD3 ADC channels z Plus input selection: z output selection: z z All analog inputs z Internal signal z external pin z selectable inverter Interrupt on: z Rising edge, Falling edge, toggle 12.
PAGE 50
13. Package Drawings The SAM3S series devices are available in LQFP, QFN and TFBGA packages. Figure 13-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
PAGE 51
Figure 13-2.
PAGE 52
Figure 13-3.
PAGE 53
Table 13-1. 48-lead LQFP Package Dimensions (in mm) Millimeter Symbol Inch Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
PAGE 54
Table 13-2. 64-lead LQFP Package Dimensions (in mm) Symbol A Millimeter Inch Min Nom Max Min Nom Max – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
PAGE 55
Figure 13-4.
PAGE 56
Table 13-3. 48-pad QFN Package Dimensions (in mm) Millimeter Symbol Inch Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.050 – – 0.002 A2 – 0.65 0.70 – 0.026 0.028 A3 b 0.20 REF 0.18 D D2 0.20 0.008 REF 0.23 0.007 7.00 bsc 5.45 E 5.60 0.008 0.009 0.276 bsc 5.75 0.215 7.00 bsc 0.220 0.226 0.276 bsc E2 5.45 5.60 5.75 0.215 0.220 0.226 L 0.35 0.40 0.45 0.014 0.016 0.018 e R 0.50 bsc 0.09 – 0.020 bsc – 0.
PAGE 57
Figure 13-5.
PAGE 58
14. Ordering Information Table 14-1.
PAGE 59
Revision History Change Request Ref. Doc. Rev Comments 6500ES Section 1. “Features”updated, “Low Power Modes” , Sleep and Backup modes, down to 1.8 µA in Backup mode Figure 8-1, "SAM3S Product Mapping", SRAM associated 1 MByte bit band region mapping changed: 0x22000000 to 0x23FFFFFF. rfo Document format updated, subsequently pagination changed 6500DS Section 14. “Ordering Information” Introduced MRL B for SAM3S1 parts.. 8545 Replace all mention to 100-ball LFBGA into 100-ball TFBGA.
PAGE 60
Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.