Datasheet
39
11011AS–ATARM–04-Oct-10
SAM3N Summary
9.13 Chip Identification
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
• JTAG ID: 0x05B2E03F
9.14 UART
•Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
9.15 PIO Controllers
• 3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79
I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of four peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change, rising edge, falling edge, low level and level interrupt
– Debouncing and Glitch filter
Table 9-1. SAM3N Chip ID Register
Chip Name CHIPID_CIDR CHIPID_EXID
ATSAM3N4C (Rev A) 0x29540960 0x0
ATSAM3N2C (Rev A) 0x29590760 0x0
ATSAM3N1C (Rev A) 0x29580560 0x0
ATSAM3N4B (Rev A) 0x29440960 0x0
ATSAM3N2B (Rev A) 0x29490760 0x0
ATSAM3N1B (Rev A) 0x29480560 0x0
ATSAM3N4A (Rev A) 0x29340960 0x0
ATSAM3N2A (Rev A) 0x29390760 0x0
ATSAM3N1A (Rev A) 0x29380560 0x0
Table 9-2. PIO available according to pin count
Version 48 pin 64 pin 100 pin
PIOA 21 32 32
PIOB 13 15 15
PIOC --32