Datasheet

37
11011AS–ATARM–04-Oct-10
SAM3N Summary
9.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
the Processor Clock HCLK
the Free running processor clock FCLK
the Cortex SysTick external clock
the Master Clock MCK, in particular to the Matrix and the memory interfaces
independent peripheral clocks, typically at the frequency of MCK
three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the Fast RC Oscillator running
at 4 MHz.
The user can trim by software the 8 and 12 MHz RC Oscillator frequency.
Figure 9-3. SAM3N4/2/1 Power Management Controller Block Diagram
The SysTick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms
with SysTick clock at 6 MHz (48 MHz/8)
9.7 Watchdog Timer
16-bit key-protected only-once-Programmable Counter
Windowed, prevents the processor to be in a dead-lock on the watchdog access
MCK
periph_clk[..]
int
SLCK
MAINCK
Prescaler
/1,/2,/4,..,/64
HCK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
SLCK
MAINCK
Prescaler
/1,/2,/4,..,/64
Programmable Clock Controller
pck[..]
ON/OFF
FCLK
SystTick
Divider
/8
PLLCK
PLLCK