Datasheet

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11011AS–ATARM–04-Oct-10
SAM3N Summary
7.5 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in Table 7-3.
7.6 Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-3. SAM3N Master to Slave Access
Masters 0 1 2
Slaves Cortex-M3 I/D Bus Cortex-M3 S Bus PDC
0 Internal SRAM - X X
1 Internal ROM X - X
2 Internal Flash X - -
3 Peripheral Bridge - X X
Table 7-4. Peripheral DMA Controller
Instance name Channel T/R 100 & 64 Pins 48 Pins
TWI0 Transmit x x
UART0 Transmit x x
USART0 Transmit x x
DAC Transmit x N/A
SPI Transmit x x
TWI0 Receive x x
UART0 Receive x x
USART0 Receive x x
ADC Receive x x
SPI Receive x x