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NOTE: This is a summary document.

The complete document is available

under NDA. For more information,

please contact your local Atmel sales

office.

Features

• Core

– ARM

Cortex

-M3 revision 2.0 running at up to 48 MHz

–Thumb

-2 instruction

– 24-bit SysTick Counter

– Nested Vector Interrupt Controller

• Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) and

ATSAM3S (48-, 64- and 100-pin version)

• Memories

– From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

single plane

– From 8 to 24 Kbytes embedded SRAM

– 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines

• System

– Embedded voltage regulator for single supply operation

– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe

operation

– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure

Detection and optional low power 32.768 kHz for RTC or device clock

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default

frequency for device startup. In-application trimming access for frequency

adjustment

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– One PLL up to 130 MHz for device clock

– Up to 10 peripheral DMA (PDC) channels

• Low Power Modes

– Sleep and Backup modes, down to 3 µA in Backup mode

– Ultra low power RTC

• Peripherals

– Up to 2 USARTs with ISO7816, IrDA

, RS-485 and SPI mode

– Two 2-wire UARTs

– 2 Two Wire Interface (I2C compatible), 1 SPI

– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and

PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for

Stepper Motor

– 4-channel 16-bit PWM

– 32-bit Real-time Timer and RTC with calendar and alarm features

– Up to 16 channels, 384 KSPS 10-bit ADC

– One 500 KSPS 10-bit DAC

• I/O

– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),

debouncing, glitch filtering and on-die Series Resistor Termination

– Three 32-bit Parallel Input/Output Controllers

• Packages

– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm / 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm

– 64-lead LQFP, 12 x 12 mm, pitch 0.5 mm / 64-pad QFN 9x9 mm, pitch 0.45 mm

– 48-lead LQFP, 9 x 9 mm, pitch 0.5 mm / 48-pad QFN 7x7 mm, pitch 0.45 mm

AT91SAM

ARM-based

Flash MCU

SAM3N Series

Summary

11011AS–ATARM–04-Oct-10

Summary of content (58 pages)

PAGE 1
Features • Core • • • • • • • – ARM® Cortex®-M3 revision 2.
PAGE 2
1. SAM3N Description Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose 16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC.
PAGE 3
SAM3N Summary 2. SAM3N Block Diagram System Controller UT VD DO JT AG VD DI N SE L SAM3N 100-pin version Block Diagram TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K Figure 2-1.
PAGE 4
System Controller UT VD DO JT AG VD DI N SE L SAM3N 64-pin version Block Diagram TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K Figure 2-2.
PAGE 5
SAM3N Summary System Controller UT VD DO JT VD DI N AG SE L SAM3N 48-pin version Block Diagramz TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K Figure 2-3.
PAGE 6
3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator, ADC and DAC Power Supply Power 1.8V to 3.6V(3) VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.65 V to 1.
PAGE 7
SAM3N Summary Table 3-1.
PAGE 8
Table 3-1.
PAGE 9
SAM3N Summary 4. Package and Pinout SAM3N4/2/1 series is pin-to-pin compatible with SAM3S products. Furthermore SAM3N4/2/1 devices have new functionalities referenced in italic inTable 4-1, Table 4-3 and Table 4-4. 4.1 4.1.1 SAM3N4/2/1C Package and Pinout 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball LFBGA Package Outline The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards.
PAGE 10
4.1.3 100-Lead LQFP Pinout Table 4-1.
PAGE 11
SAM3N Summary 4.1.4 100-ball LFBGA Pinout Table 4-2.
PAGE 12
4.2 SAM3N4/2/1B Package and Pinout Figure 4-3. Orientation of the 64-pad QFN Package 64 49 1 48 16 33 32 17 Figure 4-4.
PAGE 13
SAM3N Summary 4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3N devices are pin-to-pin compatible with SAM3S products. Furthermore, SAM3N products have new functionalities shown in italic in Table 4-3. Table 4-3.
PAGE 14
4.3 SAM3N4/2/1A Package and Pinout Figure 4-5. Orientation of the 48-pad QFN Package 48 37 1 36 12 25 13 24 TOP VIEW Figure 4-6.
PAGE 15
SAM3N Summary 4.3.1 48-Lead LQFP and QFN Pinout Table 4-4.
PAGE 16
5. Power Considerations 5.1 Power Supplies The SAM3N product has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals. Voltage ranges from 1.62V and 1.95V. • VDDIO pins: Power the Peripherals I/O lines, Backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V and 3.6V • VDDIN pin: Voltage Regulator, ADC and DAC Power Supply. Voltage ranges from 1.8V to 3.
PAGE 17
SAM3N Summary Figure 5-1. Single Supply VDDIO I/Os. Main Supply (1.8V-3.6V) ADC, DAC VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Figure 5-2. Core Externally Supplied Main Supply (1.62V-3.6V) VDDIO I/Os. Can be the same supply ADC, DAC Supply (3V-3.6V) ADC, DAC VDDIN VDDOUT VDDCORE Supply (1.62V-1.95V) Voltage Regulator VDDCORE VDDPLL Note: Restrictions With Main Supply < 3V, ADC and DAC are not usable. With Main Supply >= 3V, all peripherals are usable.
PAGE 18
Figure 5-3. Core Externally Supplied (backup battery) ADC, DAC Supply (3V-3.6V) Backup Battery VDDIO I/Os. + ADC, DAC VDDIN Main Supply IN OUT 3.3V LDO VDDOUT Voltage Regulator VDDCORE ON/OFF VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. 5.
PAGE 19
SAM3N Summary • Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. Current Consumption in Wait mode is typically 15 µA (total current consumption) if the internal voltage regulator is used or 8 µA if an external regulator is used. In this mode, the clocks of the core, peripherals and memories are stopped.
PAGE 20
5.5.4 Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Table 5-1.
PAGE 21
SAM3N Summary 5.6 Wake-up Sources The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4.
PAGE 22
5.7 Fast Start-Up The SAM3N allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast startup signal to the Power Management Controller.
PAGE 23
SAM3N Summary 6. Input/Output Lines The SAM3N has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers.
PAGE 24
Table 6-1. System I/O Configuration Pin List. SYSTEM_IO bit number Default function after reset Other function 12 ERASE PB12 Low Level at startup(1) 7 TCK/SWCLK PB7 - 6 TMS/SWDIO PB6 - 5 TDO/TRACESWO PB5 - 4 TDI PB4 - - PA7 XIN32 - - PA8 XOUT32 - - PB9 XIN - - PB8 XOUT - Notes: Constraints for normal start Configuration In Matrix User Interface Registers (Refer to the System I/O Configuration Register in the Bus Matrix section of the product datasheet.
PAGE 25
SAM3N Summary 6.3 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3N series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet. 6.
PAGE 26
7. Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single cycle 32-bit multiply. • Hardware divide. • Thumb and Debug states. • Handler and Thread modes. • Low latency ISR entry and exit. 7.
PAGE 27
SAM3N Summary 7.5 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired, and shown as “-” in Table 7-3. Table 7-3. 7.
PAGE 28
7.7 Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset.
PAGE 29
SAM3N Summary 8. Memories 8.1 Product Mapping Figure 8-1.
PAGE 30
8.2 8.2.1 Embedded Memories Internal SRAM The SAM3N4 product embeds a total of 24-Kbytes high-speed SRAM. The SAM3N2 product embeds a total of 16-Kbytes high-speed SRAM. The SAM3N1 product embeds a total of 8-Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and 0x23FF FFFF. RAM size must be configurable by calibration fuses. 8.2.
PAGE 31
SAM3N Summary 8.2.3.4 Flash Speed The user needs to set the number of wait states depending on the frequency used. For more details, refer to the AC Characteristics sub section in the product Electrical Characteristics Section. 8.2.3.5 Lock Regions Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 8-1.
PAGE 32
8.2.3.9 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST and PA0 and PA1are tied low. 8.2.3.
PAGE 33
SAM3N Summary 9. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... See the System Controller block diagram in Figure 9-1 on page 34.
PAGE 34
Figure 9-1.
PAGE 35
SAM3N Summary 9.1 System Controller and Peripherals Mapping Please refer to Figure 8-1, "SAM3N4/2/1 Product Mapping" on page 29. All the peripherals are in the bit band region and are mapped in the bit band alias region. 9.2 Power-on-Reset, Brownout and Supply Monitor The SAM3N embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 9.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO.
PAGE 36
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the software-programmable brownout detector allows detection of either a battery discharge or main voltage loss. The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator.
PAGE 37
SAM3N Summary 9.6 Power Management Controller The Power Management Controller provides all the clock signals to the system.
PAGE 38
9.8 SysTick Timer • 24-bit down counter • Self-reload capability • Flexible System timer 9.9 Real-time Timer • Real-time Timer, allowing backup of time with different accuracies – 32-bit Free-running back-up Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm register capable to generate a wake-up of the system through the Shut Down Controller 9.
PAGE 39
SAM3N Summary 9.13 Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 9-1.
PAGE 40
– Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Selection of the drive level • Synchronous output, provides Set and Clear of several I/O lines in a single write 10. Peripherals 10.1 Peripheral Identifiers Table 10-1 defines the Peripheral Identifiers of the SAM3N4/2/1.
PAGE 41
SAM3N Summary Table 10-1. Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control 25 TC2 X X Timer/Counter 2 26 TC3 X X Timer/Counter 3 27 TC4 X X Timer/Counter 4 28 TC5 X X Timer/Counter 5 29 ADC X X Analog-to-Digital Converter 30 DACC X X Digital-to-Analog Converter 31 PWM X X Pulse Width Modulation 10.
PAGE 42
10.2.1 PIO Controller A Multiplexing Table 10-2.
PAGE 43
SAM3N Summary 10.2.2 PIO Controller B Multiplexing Table 10-3.
PAGE 44
10.2.
PAGE 45
SAM3N Summary 11. Embedded Peripherals Overview 11.
PAGE 46
– Support for two PDC channels with connection to receiver and transmitter (for UART0 only) 11.4 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.
PAGE 47
SAM3N Summary – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels • Quadrature decoder – Advanced line filtering – Position/revolution/speed • 2-bit Gray Up/Down Counter for Stepper Motor 11.
PAGE 48
12. Package Drawings The SAM3N series devices are available in LQFP, QFN and LFBGA packages. Figure 12-1. 100-lead LQFP Package Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
PAGE 49
SAM3N Summary Figure 12-2.
PAGE 50
Figure 12-3.
PAGE 51
SAM3N Summary Table 12-1. 48-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.
PAGE 52
Table 12-2. 64-lead LQFP Package Dimensions (in mm) Symbol Millimeter Inch Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
PAGE 53
SAM3N Summary Figure 12-4.
PAGE 54
Table 12-3. 48-pad QFN Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.050 – – 0.002 A2 – 0.65 0.70 – 0.026 0.028 A3 b 0.20 REF 0.18 D D2 0.20 0.008 REF 0.23 0.007 7.00 bsc 5.45 E 5.60 0.008 0.009 0.276 bsc 5.75 0.215 7.00 bsc 0.220 0.226 0.276 bsc E2 5.45 5.60 5.75 0.215 0.220 0.226 L 0.35 0.40 0.45 0.014 0.016 0.018 e R 0.50 bsc 0.09 – 0.020 bsc – 0.
PAGE 55
SAM3N Summary Figure 12-5.
PAGE 56
13. Ordering Information Table 13-1.
PAGE 57
SAM3N Summary Revision History Doc. Rev Comments 11011AS First issue Change Request Ref.
PAGE 58
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