Datasheet

90
11011B–ATARM–21-Feb-12
SAM3N
[Rn, #offset]!
10.12.2.5 Post-indexed addressing
The address obtained from the register Rn is used as the address for the memory access. The
offset value is added to or subtracted from the address, and written back into the register Rn.
The assembly language syntax for this mode is:
[Rn], #offset
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can
either be signed or unsigned. See “Address alignment” on page 83.
Table 10-18 shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
10.12.2.6 Restrictions
For load instructions:
• Rt can be SP or PC for word loads only
• Rt must be different from Rt2 for two-word loads
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution
• a branch occurs to the address created by changing bit[0] of the loaded value to 0
• if the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
• Rt can be SP for word stores only
• Rt must not be PC
• Rn must not be PC
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
10.12.2.7 Condition flags
These instructions do not change the flags.
Table 10-18. Offset ranges
Instruction type Immediate offset Pre-indexed Post-indexed
Word, halfword, signed
halfword, byte, or signed
byte
−255 to 4095 −255 to 255 −255 to 255
Two w o r d s
multiple of 4 in the
range −1020 to
1020
multiple of 4 in the
range −1020 to
1020
multiple of 4 in the
range −1020 to
1020