Datasheet

80
11011B–ATARM–21-Feb-12
SAM3N
Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be
1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3
processor only supports Thumb instructions.
10.11.3 Flexible second operand
Many general data processing instructions have a flexible second operand. This is shown as
Operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a:
• “Constant”
• “Register with optional shift” on page 80
10.11.3.1 Constant
You specify an Operand2 constant in the form:
#constant
where constant can be:
• any constant that can be produced by shifting an 8-bit value left by any number of bits within
a 32-bit word
• any constant of the form 0x00XY00XY
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY.
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values.
These are described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS,
EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is
greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect
the carry flag if Operand2 is any other constant.
10.11.3.2 Instruction substitution
Your assembler might be able to produce an equivalent instruction in cases where you specify a
constant that is not permitted. For example, an assembler might assemble the instruction CMP
Rd , #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.
10.11.3.3 Register with optional shift
You specify an Operand2 register in the form:
Rm {, shift}
where:
Rm is the register holding the data for the second operand.
shift is an optional shift to be applied to Rm. It can be one of:
ASR #n arithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL #n logical shift left n bits, 1 ≤ n ≤ 31.